Inventor · disambiguated record
Satish Damaraju
Also filed as: DAMARAJU SATISH · DAMARAJU SATISH K
24 granted patents·5 pending applications·104 citations·filing 2003–2022
94Inventor score
Top patents by PatentIndex Score
29 records- 0193US10473718B2Multibit vectored sequential with scanINTEL CORP·Filed 2017·Granted Nov 12, 2019·4 cites·22 claims
- 0292US9823719B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2013·Granted Nov 21, 2017·11 cites·21 claims
- 0389US10429913B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2018·Granted Oct 1, 2019·4 cites·20 claims
- 0489US10409346B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2018·Granted Sep 10, 2019·4 cites·20 claims
- 0589US10146283B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2017·Granted Dec 4, 2018·4 cites·20 claims
- 0685US11157052B2Controlling power delivery to a processor via a bypassINTEL CORP·Filed 2019·Granted Oct 26, 2021·2 cites·20 claims
- 0784US7130236B2Low power delay controlled zero sensitive sense amplifierINTEL CORP·Filed 2005·Granted Oct 31, 2006·17 cites·25 claims
- 0881US8713256B2Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performanceSODHI INDER M·Filed 2011·Granted Apr 29, 2014·4 cites·19 claims
- 0979US7136984B2Low power cache architectureINTEL CORP·Filed 2004·Granted Nov 14, 2006·23 cites·20 claims
- 1077US11398814B2Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flopINTEL CORP·Filed 2020·Granted Jul 26, 2022·1 cites·16 claims
- 1175US11687135B2Controlling power delivery to a processor via a bypassTAHOE RES LTD·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 1275US7689772B2Power-performance modulation in caches using a smart least recently used schemeINTEL CORP·Filed 2006·Granted Mar 30, 2010·11 cites·24 claims
- 1374US11442103B2Multibit vectored sequential with scanINTEL CORP·Filed 2021·Granted Sep 13, 2022·0 cites·22 claims
- 1474US9075741B2Dynamic error handling using parity and redundant rowsKOKER ALTUG·Filed 2011·Granted Jul 7, 2015·4 cites·4 claims
- 1562US7457917B2Reducing power consumption in a sequential cacheINTEL CORP·Filed 2004·Granted Nov 25, 2008·11 cites·14 claims
- 1660US11009549B2Multibit vectored sequential with scanINTEL CORP·Filed 2019·Granted May 18, 2021·0 cites·24 claims
- 1760US9336008B2Shared function multi-ported ROM apparatus and methodDAMARAJU SATISH K·Filed 2011·Granted May 10, 2016·1 cites·19 claims
- 1857US12436467B2Simulating die rotation to minimize area overhead of reticle stitching for stacked diesINTEL CORP·Filed 2021·Granted Oct 7, 2025·0 cites·18 claims
- 1955US8356202B2System and method for reducing power consumption in a device using register filesINTEL CORP·Filed 2008·Granted Jan 15, 2013·1 cites·15 claims
- 2053US2023387074A1Integrated circuit assemblies having interconnection bridges spanning reticle boundary / dicing streets of monolithic structures thereinINTEL CORP·Filed 2022·Application pending·0 cites
- 2150US7155574B2Look ahead LRU array update scheme to minimize clobber in sequentially accessed memoryINTEL CORP·Filed 2006·Granted Dec 26, 2006·0 cites·40 claims
- 2248US2022197806A1High speed memory system integrationINTEL CORP·Filed 2020·Application pending·0 cites
- 2345US2004268099A1Look ahead LRU array update scheme to minimize clobber in sequentially accessed memorySMITH PETER J·Filed 2003·Application pending·0 cites
- 2442US8448010B2Increasing memory bandwidth in processor-based systemsDAMARAJU SATISH K·Filed 2009·Granted May 21, 2013·2 cites·14 claims
- 2541US2018203694A1Execution Unit with Selective Instruction Pipeline BypassINTEL CORP·Filed 2017·Application pending·0 cites
- 2639US8345491B2Memory cell writeINTEL CORP·Filed 2011·Granted Jan 1, 2013·0 cites·20 claims
- 2738US8050116B2Memory cell writeINTEL CORP·Filed 2009·Granted Nov 1, 2011·0 cites·20 claims
- 2838US2011149661A1Memory array having extended write operationRAJWANI IQBAL R·Filed 2009·Application pending·0 cites
- 2928US7805619B2Circuit technique to reduce leakage during reduced power modeINTEL CORP·Filed 2006·Granted Sep 28, 2010·0 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →