Inventor · disambiguated record
Saurabh Desai
Also filed as: DESAI SAURABH · DESAI SAURABH M
10 granted patents·107 citations·filing 1992–2012
88Inventor score
Top patents by PatentIndex Score
10 records- 0188US7719048B1Heating element for enhanced E2PROMNAT SEMICONDUCTOR CORP·Filed 2007·Granted May 18, 2010·13 cites·5 claims
- 0280US7663173B1Non-volatile memory cell with poly filled trench as control gate and fully isolated substrate as charge storageNAT SEMICONDUCTOR CORP·Filed 2007·Granted Feb 16, 2010·12 cites·19 claims
- 0379US8247862B2Method of enhancing charge storage in an E2PROM cellBABCOCK JEFF A·Filed 2010·Granted Aug 21, 2012·8 cites·2 claims
- 0474US5262345AComplimentary bipolar/CMOS fabrication methodANALOG DEVICES INC·Filed 1992·Granted Nov 16, 1993·58 cites·4 claims
- 0572US7919807B1Non-volatile memory cell with heating elementNAT SEMICONDUCTOR CORP·Filed 2007·Granted Apr 5, 2011·4 cites·11 claims
- 0672US7919805B1Non-volatile memory cell with two capacitors and one PNP transistor and a method of forming such a cell in a 1-poly SOI technologyNAT SEMICONDUCTOR CORP·Filed 2007·Granted Apr 5, 2011·8 cites·10 claims
- 0762US8183621B2Non-volatile memory cell having a heating element and a substrate-based control gateBABCOCK JEFFREY A·Filed 2011·Granted May 22, 2012·1 cites·19 claims
- 0860US8207559B2Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structuresBABCOCK JEFFREY A·Filed 2009·Granted Jun 26, 2012·2 cites·2 claims
- 0956US7425741B1EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusionNAT SEMICONDUCTOR CORP·Filed 2005·Granted Sep 16, 2008·1 cites·9 claims
- 1052US8669157B2Non-volatile memory cell having a heating element and a substrate-based control gateBABCOCK JEFFREY A·Filed 2012·Granted Mar 11, 2014·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →