Inventor · disambiguated record
Sadanand V. Deshpande
Also filed as: DESHPANDE SADANAND · DESHPANDE SADANAND V · DESHPANDE SADANAND VINAYAK
19 granted patents·7 pending applications·1,002 citations·filing 2001–2018
95Inventor score
Top patents by PatentIndex Score
26 records- 0198US7595010B2Method for producing a doped nitride film, doped oxide film and other doped filmsIBM·Filed 2007·Granted Sep 29, 2009·57 cites·1 claims
- 0298US7361611B2Doped nitride film, doped oxide film and other doped filmsIBM·Filed 2006·Granted Apr 22, 2008·55 cites·14 claims
- 0398US6864041B2Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etchingIBM·Filed 2001·Granted Mar 8, 2005·538 cites·12 claims
- 0495US6790733B1Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacerIBM·Filed 2003·Granted Sep 14, 2004·122 cites·23 claims
- 0591US6930030B2Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thicknessIBM·Filed 2003·Granted Aug 16, 2005·57 cites·20 claims
- 0687US7407875B2Low resistance contact structure and fabrication thereofIBM·Filed 2006·Granted Aug 5, 2008·16 cites·3 claims
- 0786US6512266B1Method of fabricating SiO2 spacers and annealing capsIBM·Filed 2001·Granted Jan 28, 2003·40 cites·24 claims
- 0885US6884734B2Vapor phase etch trim structure with top etch blocking layerIBM·Filed 2001·Granted Apr 26, 2005·38 cites·38 claims
- 0981US7700425B2Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plugIBM·Filed 2006·Granted Apr 20, 2010·8 cites·16 claims
- 1076US6960510B2Method of making sub-lithographic featuresIBM·Filed 2002·Granted Nov 1, 2005·21 cites·11 claims
- 1176US6887798B2STI stress modification by nitrogen plasma treatment for improving performance in small width devicesIBM·Filed 2003·Granted May 3, 2005·16 cites·12 claims
- 1274US7344983B2Clustered surface preparation for silicide and metal contactsIBM·Filed 2005·Granted Mar 18, 2008·4 cites·5 claims
- 1370US7479688B2STI stress modification by nitrogen plasma treatment for improving performance in small width devicesIBM·Filed 2004·Granted Jan 20, 2009·11 cites·18 claims
- 1470US6903023B2In-situ plasma etch for TERA hard mask materialsIBM·Filed 2002·Granted Jun 7, 2005·15 cites·21 claims
- 1562US7354867B2Etch process for improving yield of dielectric contacts on nickel silicidesIBM·Filed 2005·Granted Apr 8, 2008·1 cites·13 claims
- 1652US9451684B2Dual pulse driven extreme ultraviolet (EUV) radiation source methodIBM·Filed 2016·Granted Sep 20, 2016·0 cites·19 claims
- 1752US2009008785A1Etch process for improving yield of dielectric contacts on nickel silicidesIBM·Filed 2008·Application pending·0 cites
- 1852US2008156257A1Clustered surface preparation for silicide and metal contactsIBM·Filed 2007·Application pending·0 cites
- 1950US11917998B2Disinfectant for hatcheriesCEVA SANTE ANIMALE·Filed 2018·Granted Mar 5, 2024·0 cites·14 claims
- 2050US9301381B1Dual pulse driven extreme ultraviolet (EUV) radiation source utilizing a droplet comprising a metal core with dual concentric shells of buffer gasIBM·Filed 2014·Granted Mar 29, 2016·0 cites·20 claims
- 2149US7091081B2Method for patterning a semiconductor regionIBM·Filed 2004·Granted Aug 15, 2006·3 cites·30 claims
- 2245US2005287747A1Doped nitride film, doped oxide film and other doped filmsIBM·Filed 2004·Application pending·0 cites
- 2343US2007249149A1Improved thermal budget using nickel based silicides for enhanced semiconductor device performanceIBM·Filed 2006·Application pending·0 cites
- 2441US2008188089A1Method for reducing top notching effects in pre-doped gate structuresIBM·Filed 2007·Application pending·0 cites
- 2538US2005054169A1Method of manufacture of raised source drain mosfet with top notched gate structure filled with dielectric plug in and device manufactured therebyIBM·Filed 2003·Application pending·0 cites
- 2635US2005275034A1A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performanceIBM·Filed 2004·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Sadanand V. Deshpande files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →