Inventor · disambiguated record
Sabareesh Ganapathy
Also filed as: GANAPATHY SABAREESH
7 granted patents·8 pending applications·10 citations·filing 2017–2025
78Inventor score
Files withINTEL CORP15
Top patents by PatentIndex Score
15 records- 0190US12014265B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2023·Granted Jun 18, 2024·1 cites·20 claims
- 0287US11636327B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2017·Granted Apr 25, 2023·6 cites·20 claims
- 0384US2025384257A1Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2025·Application pending·0 cites
- 0483US12346694B2Register file for systolic arrayINTEL CORP·Filed 2021·Granted Jul 1, 2025·1 cites·20 claims
- 0582US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 0681US12380326B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2024·Granted Aug 5, 2025·0 cites·20 claims
- 0778US11977895B2Hierarchical thread scheduling based on multiple barriersINTEL CORP·Filed 2020·Granted May 7, 2024·1 cites·20 claims
- 0877US2025390307A1Register file for systolic arrayINTEL CORP·Filed 2025·Application pending·0 cites
- 0973US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 1064US12399685B2Systolic array having support for output sparsityINTEL CORP·Filed 2021·Granted Aug 26, 2025·0 cites·20 claims
- 1151US2025068423A1Instruction encoding to implement increased register capacity per threadINTEL CORP·Filed 2023·Application pending·0 cites
- 1245US2023104845A1Graphics processor memory access architecture with address sortingINTEL CORP·Filed 2021·Application pending·0 cites
- 1344US2023086275A1Emulation of floating point calculationINTEL CORP·Filed 2021·Application pending·0 cites
- 1442US2019324757A1Maintaining high temporal cache locality between independent threads having the same access patternINTEL CORP·Filed 2018·Application pending·0 cites
- 1542US2021382717A1Hierarchical thread schedulingINTEL CORP·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →