Inventor · disambiguated record
Sanjiv Garg
Also filed as: GARG SANJIV
72 granted patents·2 pending applications·2,572 citations·filing 1991–2009
99Inventor score
Technology areasG06F
Files withSEIKO EPSON CORP63GARG SANJIV3TRANSMETA CORP3IADONATO KEVIN R1INTELLECTUAL VENTURE FUNDING LLC1
Top patents by PatentIndex Score
74 records- 0195US7739482B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2006·Granted Jun 15, 2010·26 cites·18 claims
- 0295US5560032AHigh-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·193 cites·29 claims
- 0395US5539911AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1992·Granted Jul 23, 1996·133 cites·56 claims
- 0494US8074052B2System and method for assigning tags to control instruction processing in a superscalar processorIADONATO KEVIN R·Filed 2008·Granted Dec 6, 2011·37 cites·18 claims
- 0593US5497499ASuperscalar risc instruction schedulingSEIKO EPSON CORP·Filed 1994·Granted Mar 5, 1996·120 cites·16 claims
- 0692US6775761B2System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessorSEIKO EPSON CORP·Filed 2002·Granted Aug 10, 2004·51 cites·47 claims
- 0792US6647485B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2001·Granted Nov 11, 2003·42 cites·40 claims
- 0891US5689720AHigh-performance superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1996·Granted Nov 18, 1997·90 cites·11 claims
- 0991US5493687ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1991·Granted Feb 20, 1996·103 cites·5 claims
- 1090US6965987B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2003·Granted Nov 15, 2005·43 cites·58 claims
- 1190US5560035ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·105 cites·8 claims
- 1289US6986024B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jan 10, 2006·28 cites·24 claims
- 1389US6360309B1System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2000·Granted Mar 19, 2002·36 cites·18 claims
- 1488US6915412B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jul 5, 2005·25 cites·26 claims
- 1587US7685402B2RISC microprocessor architecture implementing multiple typed register setsGARG SANJIV·Filed 2007·Granted Mar 23, 2010·10 cites·12 claims
- 1687US6948052B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Sep 20, 2005·23 cites·39 claims
- 1787US5961629AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1998·Granted Oct 5, 1999·135 cites·27 claims
- 1886US7721070B2High-performance, superscalar-based computer system with out-of-order instruction executionNGUYEN LE TRONG·Filed 2008·Granted May 18, 2010·10 cites·21 claims
- 1986US7162610B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Jan 9, 2007·21 cites·35 claims
- 2086US6412064B1System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessorSEIKO EPSON CORP·Filed 2000·Granted Jun 25, 2002·28 cites·41 claims
- 2185US7558945B2System and method for register renamingSEIKO EPSON CORP·Filed 2005·Granted Jul 7, 2009·8 cites·24 claims
- 2285US7051187B2Superscalar RISC instruction schedulingTRANSMETA CORP·Filed 2002·Granted May 23, 2006·24 cites·19 claims
- 2385US6959375B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Oct 25, 2005·19 cites·10 claims
- 2484US6934829B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Aug 23, 2005·17 cites·21 claims
- 2583US5590295ASystem and method for register renamingSEIKO EPSON CORP·Filed 1995·Granted Dec 31, 1996·66 cites·17 claims
- 2682US6757808B2System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2002·Granted Jun 29, 2004·19 cites·20 claims
- 2782US5448705ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1993·Granted Sep 5, 1995·79 cites·3 claims
- 2881US7523296B2System and method for handling exceptions and branch mispredictions in a superscalar microprocessorSEIKO EPSON CORP·Filed 2005·Granted Apr 21, 2009·6 cites·24 claims
- 2980US7979678B2System and method for register renamingSEIKO EPSON CORP·Filed 2009·Granted Jul 12, 2011·5 cites·34 claims
- 3080US7555632B2High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2005·Granted Jun 30, 2009·6 cites·23 claims
- 3180US6941447B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Sep 6, 2005·13 cites·23 claims
- 3280US6128723AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Oct 3, 2000·42 cites·27 claims
- 3379US7941635B2High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2006·Granted May 10, 2011·5 cites·5 claims
- 3479US7028161B2High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2001·Granted Apr 11, 2006·17 cites·39 claims
- 3579US6038654AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Mar 14, 2000·39 cites·80 claims
- 3679US5481685ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1994·Granted Jan 2, 1996·66 cites·16 claims
- 3778US8019975B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2005·Granted Sep 13, 2011·5 cites·59 claims
- 3878US5737624ASuperscalar risc instruction schedulingSEIKO EPSON CORP·Filed 1996·Granted Apr 7, 1998·51 cites·19 claims
- 3977US7043624B2System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2004·Granted May 9, 2006·13 cites·18 claims
- 4077US6092181AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1997·Granted Jul 18, 2000·37 cites·62 claims
- 4177US5826055ASystem and method for retiring instructions in a superscalar microprocessorSEIKO EPSON CORP·Filed 1995·Granted Oct 20, 1998·82 cites·52 claims
- 4277US5604912ASystem and method for assigning tags to instructions to control instruction executionSEIKO EPSON CORP·Filed 1992·Granted Feb 18, 1997·62 cites·40 claims
- 4376US6922772B2System and method for register renamingSEIKO EPSON CORP·Filed 2002·Granted Jul 26, 2005·12 cites·9 claims
- 4476US6920548B2System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessorSEIKO EPSON CORP·Filed 2004·Granted Jul 19, 2005·12 cites·58 claims
- 4576US6408375B2System and method for register renamingSEIKO EPSON CORP·Filed 2001·Granted Jun 18, 2002·13 cites·19 claims
- 4676US6272619B1High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·34 cites·80 claims
- 4776US6256720B1High performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Jul 3, 2001·34 cites·80 claims
- 4876US5838986ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1997·Granted Nov 17, 1998·42 cites·30 claims
- 4975US6970995B2System and method for register renamingSEIKO EPSON CORP·Filed 2002·Granted Nov 29, 2005·12 cites·9 claims
- 5075US6101594AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Aug 8, 2000·31 cites·31 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →