Inventor · disambiguated record
Saket K. Goyal
Also filed as: GOYAL SAKET · GOYAL SAKET K
8 granted patents·1 pending application·86 citations·filing 2001–2012
86Inventor score
Top patents by PatentIndex Score
9 records- 0191US7831876B2Testing a circuit with compressed scan chain subsetsLSI CORP·Filed 2007·Granted Nov 9, 2010·25 cites·11 claims
- 0278US8694951B1Core wrapping in the presence of an embedded wrapped coreLSI CORP·Filed 2012·Granted Apr 8, 2014·11 cites·18 claims
- 0378US7188330B2Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creationLSI LOGIC CORP·Filed 2004·Granted Mar 6, 2007·30 cites·18 claims
- 0460US7006962B1Distributed delay prediction of multi-million gate deep sub-micron ASIC designsLSI LOGIC CORP·Filed 2001·Granted Feb 28, 2006·10 cites·19 claims
- 0549US7360133B2Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis toolLSI LOGIC CORP·Filed 2004·Granted Apr 15, 2008·4 cites·24 claims
- 0648US7284211B2Extensible IO testing implementationLSI CORP·Filed 2003·Granted Oct 16, 2007·2 cites·14 claims
- 0747US7181359B2Method and system of generic implementation of sharing test pins with I/O cellsLSI LOGIC CORP·Filed 2004·Granted Feb 20, 2007·4 cites·17 claims
- 0843US7047470B2Flexible and extensible implementation of sharing test pins in ASICLSI LOGIC CORP·Filed 2003·Granted May 16, 2006·0 cites·16 claims
- 0928US2011279171A1Electrically programmable fuse controller for integrated circuit identification, method of operation thereof and integrated circuit incorporating the sameCAO LIHUI·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →