Inventor · disambiguated record
Sam Karikalan
Also filed as: KARIKALAN SAM · KARIKALAN SAM KOMARAPALAYAM
6 granted patents·10 pending applications·15 citations·filing 2016–2025
75Inventor score
Top patents by PatentIndex Score
16 records- 0193US10008439B2Thin recon interposer package without TSV for fine input/output pitch fan-outAVAGO TECHNOLOGIES GENERAL IP·Filed 2016·Granted Jun 26, 2018·10 cites·20 claims
- 0291US11906802B2Photonics integration in semiconductor packagesAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Feb 20, 2024·2 cites·20 claims
- 0384US10615110B2Thin recon interposer package without TSV for fine input/output pitch fan-outAVAGO TECH INT SALES PTE LID·Filed 2018·Granted Apr 7, 2020·3 cites·20 claims
- 0474US2025096108A1Cantilevered power planes to provide a return current path for high-speed signalsAVAGO TECH INT SALES PTE LID·Filed 2024·Application pending·0 cites
- 0573US2024151921A1Photonics Integration in Semiconductor PackagesAVAGO TECH INT SALES PTE LID·Filed 2024·Application pending·0 cites
- 0671US2025279341A1Multilayer Cores, Variable Width Vias, and Offset ViasAVAGO TECH INT SALES PTE LID·Filed 2025·Application pending·0 cites
- 0764US12191243B2Cantilevered power planes to provide a return current path for high-speed signalsAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 0862US2023352383A1Multilayer Cores, Variable Width Vias, and Offset ViasAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 0960US12463319B2Integrated antennas on side wall of 3D stacked dieAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Nov 4, 2025·0 cites·8 claims
- 1053US2024145392A1Substrate with Differing Dielectric ConstantsAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 1152US2024128156A1Microfluidic Channels for Cooling Hybrid Bonded InterfacesAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 1251US2024038641A1Elastomer Interconnection Substrate LayerAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 1351US2024038645A1Semiconductor Package Interconnection StructureAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 1451US2024038613A1Edge Seal for Bonded Stacks of Different Size Semiconductor DevicesAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
- 1550US12438062B2Polymerized thermal interface material with surface modified liquid metal spheres and method of makingAVAGO TECH INT SALES PTE LID·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 1650US2023369267A13D Packaging Heterogeneous Area Array InterconnectionsAVAGO TECH INT SALES PTE LID·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →