Inventor · disambiguated record
Sakthivel Komarasamy Pullagoundapatti
Also filed as: PULLAGOUNDAPATTI SAKTHIVEL K · PULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY
3 granted patents·3 pending applications·1 citations·filing 2009–2012
47Inventor score
Technology areasG06F
Files withPULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY3LSI CORP1PULLAGOUNDAPATTI SAKTHIVEL K1VALLAPANENI VENKAT RAO1
Top patents by PatentIndex Score
6 records- 0148US8583844B2System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecturePULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2011·Granted Nov 12, 2013·1 cites·16 claims
- 0238US7984212B2System and method for utilizing first-in-first-out (FIFO) resources for handling differences in data rates between peripherals via a merge module that merges FIFO channelsLSI CORP·Filed 2009·Granted Jul 19, 2011·0 cites·18 claims
- 0334US2014068125A1Memory throughput improvement using address interleavingPULLAGOUNDAPATTI SAKTHIVEL K·Filed 2012·Application pending·0 cites
- 0432US8533377B2System and method for allocating transaction ID in a system with a plurality of processing modulesVALLAPANENI VENKAT RAO·Filed 2011·Granted Sep 10, 2013·0 cites·18 claims
- 0527US2014006644A1Address Remapping Using Interconnect Routing Identification BitsPULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2012·Application pending·0 cites
- 0627US2012303897A1Configurable set associative cache way architecturePULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →