Inventor · disambiguated record
Sajish Sajayan
Also filed as: SAJAYAN SAJISH
7 granted patents·1 pending application·35 citations·filing 2008–2010
83Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0186US8112652B2Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bankSAJAYAN SAJISH·Filed 2009·Granted Feb 7, 2012·12 cites·3 claims
- 0283US7945875B2Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compilerTEXAS INSTRUMENTS INC·Filed 2008·Granted May 17, 2011·16 cites·8 claims
- 0370US8683133B2Termination of prefetch requests in shared memory controllerSAJAYAN SAJISH·Filed 2009·Granted Mar 25, 2014·3 cites·4 claims
- 0466US8301928B2Automatic wakeup handling on access in shared memory controllerSAJAYAN SAJISH·Filed 2009·Granted Oct 30, 2012·2 cites·3 claims
- 0565US8078897B2Power management in federated/distributed shared memory architectureSAJAYAN SAJISH·Filed 2009·Granted Dec 13, 2011·2 cites·4 claims
- 0654US8683134B2Upgrade of low priority prefetch requests to high priority real requests in shared memory controllerSAJAYAN SAJISH·Filed 2009·Granted Mar 25, 2014·0 cites·2 claims
- 0752US8117398B2Prefetch termination at powered down memory bank boundary in shared memory controllerSAJAYAN SAJISH·Filed 2009·Granted Feb 14, 2012·0 cites·4 claims
- 0831US2011280314A1Slice encoding and decoding processors, circuits, devices, systems and processesSANKARAN JAGADEESH·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →