Inventor · disambiguated record
Sanjiv Shah
Also filed as: SHAH SANJIV · SHAH SANJIV M
16 granted patents·7 pending applications·384 citations·filing 1996–2012
94Inventor score
Top patents by PatentIndex Score
23 records- 0191US8108863B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2005·Granted Jan 31, 2012·30 cites·24 claims
- 0287US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 0387US7571301B2Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processorsINTEL CORP·Filed 2006·Granted Aug 4, 2009·23 cites·27 claims
- 0485US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 0585US6286130B1Software implemented method for automatically validating the correctness of parallel computer programsINTEL CORP·Filed 1997·Granted Sep 4, 2001·131 cites·25 claims
- 0681US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 0775US5812852ASoftware implemented method for thread-privatizing user-specified global storage objects in parallel computer programs via program transformationKUCK & ASSOCIATES INC·Filed 1996·Granted Sep 22, 1998·81 cites·12 claims
- 0872US7328433B2Methods and apparatus for reducing memory latency in a software applicationINTEL CORP·Filed 2003·Granted Feb 5, 2008·19 cites·34 claims
- 0969US8689215B2Structured exception handling for application-managed thread unitsHANKINS RICHARD A·Filed 2006·Granted Apr 1, 2014·5 cites·28 claims
- 1069US8079035B2Data structure and management techniques for local user-level thread dataHANKINS RICHARD A·Filed 2005·Granted Dec 13, 2011·5 cites·23 claims
- 1168US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 1266US7069556B2Method and apparatus for implementing a parallel construct comprised of a single taskINTEL CORP·Filed 2001·Granted Jun 27, 2006·11 cites·12 claims
- 1365US6792599B2Method and apparatus for an atomic operation in a parallel computing environmentINTEL CORP·Filed 2001·Granted Sep 14, 2004·12 cites·29 claims
- 1464US8839258B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2012·Granted Sep 16, 2014·1 cites·29 claims
- 1564US7500242B2Low-contention lockINTEL CORP·Filed 2003·Granted Mar 3, 2009·11 cites·44 claims
- 1656US7703094B2Adaptive and dynamic filtering of threaded programsINTEL CORP·Filed 2004·Granted Apr 20, 2010·9 cites·14 claims
- 1743US2003066056A1Method and apparatus for accessing thread-privatized global storage objectsFiled 2001·Application pending·0 cites
- 1842US2006225031A1Method and apparatus for accessing thread-privatized global storage objectsPETERSEN PAUL M·Filed 2006·Application pending·0 cites
- 1941US2005081206A1Methods and apparatus for profiling threaded programsFiled 2003·Application pending·0 cites
- 2040US2007074217A1Scheduling optimizations for user-level threadsRAKVIC RYAN·Filed 2005·Application pending·0 cites
- 2136US2003135535A1Transferring data between threads in a multiprocessing computer systemFiled 2002·Application pending·0 cites
- 2236US2003126589A1Providing parallel computing reduction operationsFiled 2002·Application pending·0 cites
- 2334US2003088856A1Method and apparatus for obtaining the address of a descriptorFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →