Inventor · disambiguated record
Sarabjeet Singh
Also filed as: SINGH SARABJEET
3 granted patents·9 pending applications·32 citations·filing 2004–2018
69Inventor score
Top patents by PatentIndex Score
12 records- 0187US8872587B2Generating negative impedance compensationIBM·Filed 2013·Granted Oct 28, 2014·15 cites·9 claims
- 0284US7383490B2Methods and apparatus using commutative error detection values for fault isolation in multiple node computersIBM·Filed 2005·Granted Jun 3, 2008·15 cites·41 claims
- 0377US10802995B2Unified address space for multiple hardware accelerators using dedicated low latency linksXILINX INC·Filed 2018·Granted Oct 13, 2020·2 cites·20 claims
- 0452US2015356543A1System and method for associating identifiers with transactionsCASHEDGE INC·Filed 2015·Application pending·0 cites
- 0552US2005187867A1System and method for associating identifiers with transactionsFiled 2005·Application pending·0 cites
- 0648US2019122245A1Systems and methods for displaying an order discount on a user interfaceWALMART APOLLO LLC·Filed 2018·Application pending·0 cites
- 0746US2018211201A1Systems and methods for optimizing outbound shipping capacityWAL MART STORES INC·Filed 2017·Application pending·0 cites
- 0846US2018197132A1Systems and methods for determining product shipping costs for products sold from an online retailerWAL MART STORES INC·Filed 2017·Application pending·0 cites
- 0942US2004236653A1System and method for associating identifiers with dataFiled 2004·Application pending·0 cites
- 1030US2009302915A1Low Power and Full Rail-to-Rail Swing Pseudo CML LatchSINGH SARABJEET·Filed 2008·Application pending·0 cites
- 1130US2009302893A1High Speed "Pseudo" Current Mode Logic (CML) Integrated Circuit Memory LatchSINGH SARABJEET·Filed 2008·Application pending·0 cites
- 1230US2009302916A1Low Power and Full Swing Pseudo CML Latched Logic-GatesSINGH SARABJEET·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →