Inventor · disambiguated record
Salvatore N. Storino
Also filed as: STORINO SALVATORE N · STORINO SALVATORE NICKOLAS
13 granted patents·116 citations·filing 1995–2008
90Inventor score
Files withIBM13
Top patents by PatentIndex Score
13 records- 0185US6188247B1Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elementsIBM·Filed 1999·Granted Feb 13, 2001·56 cites·37 claims
- 0261US6150869AMethod and apparatus for body control in silicon-on-insulator (SOI) domino circuitsIBM·Filed 1999·Granted Nov 21, 2000·17 cites·16 claims
- 0354US6094072AMethods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuitsIBM·Filed 1999·Granted Jul 25, 2000·15 cites·12 claims
- 0453US6462581B1Programmable timing boundary in dynamic circuitsIBM·Filed 2000·Granted Oct 8, 2002·6 cites·14 claims
- 0546US6049218ASemiconductor device having embedded test device for testing design specificationsIBM·Filed 1998·Granted Apr 11, 2000·9 cites·8 claims
- 0641US6271686B2Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuitsIBM·Filed 2000·Granted Aug 7, 2001·1 cites·22 claims
- 0738US7839715B2SerDes double rate bitline with interlock to block precharge captureIBM·Filed 2008·Granted Nov 23, 2010·0 cites·1 claims
- 0838US6111422AMethod of testing susceptibility to failure of functional circuitry embodied in an integrated circuitIBM·Filed 1999·Granted Aug 29, 2000·5 cites·20 claims
- 0936US7489039B2Metal fill region of a semiconductor chipIBM·Filed 2006·Granted Feb 10, 2009·0 cites·2 claims
- 1035US6808998B2Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuitsIBM·Filed 2000·Granted Oct 26, 2004·0 cites·10 claims
- 1133US6005406ATest device and method facilitating aggressive circuit designIBM·Filed 1995·Granted Dec 21, 1999·3 cites·10 claims
- 1232US6365934B1Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuitsIBM·Filed 1999·Granted Apr 2, 2002·2 cites·18 claims
- 1331US6278157B1Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elementsIBM·Filed 1999·Granted Aug 21, 2001·2 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →