Inventor · disambiguated record
Salvatore N. Storino
Also filed as: STORINO SALVATORE N · STORINO SALVATORE NICHOLAS
14 granted patents·5 pending applications·623 citations·filing 1996–2012
93Inventor score
Top patents by PatentIndex Score
19 records- 0195US7224633B1eFuse sense circuitIBM·Filed 2005·Granted May 29, 2007·49 cites·17 claims
- 0294US6748556B1Changing the thread capacity of a multithreaded computer processorIBM·Filed 2000·Granted Jun 8, 2004·118 cites·16 claims
- 0393US6681345B1Field protection against thread loss in a multithreaded computer processorIBM·Filed 2000·Granted Jan 20, 2004·103 cites·10 claims
- 0491US5778243AMulti-threaded cell for a memoryIBM·Filed 1996·Granted Jul 7, 1998·211 cites·35 claims
- 0589US6617518B2Enhanced flex cableJDS UNIPHASE CORPORATON·Filed 2001·Granted Sep 9, 2003·74 cites·16 claims
- 0682US6775624B2Method and apparatus for estimating remaining life of a productIBM·Filed 2001·Granted Aug 10, 2004·25 cites·6 claims
- 0778US8780604B2State sensing system for eFuse memoryLIAO CHIHHUNG·Filed 2012·Granted Jul 15, 2014·9 cites·20 claims
- 0871US7268590B2Method and apparatus for implementing subthreshold leakage reduction in LSDLIBM·Filed 2005·Granted Sep 11, 2007·7 cites·15 claims
- 0964US6163173AMethod and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performanceIBM·Filed 1999·Granted Dec 19, 2000·19 cites·16 claims
- 1055US7142061B2Balanced single ended to differential signal converterIBM·Filed 2005·Granted Nov 28, 2006·3 cites·20 claims
- 1149US2010266081A1System and Method for Double Rate Clocking Pulse Generation With Mistrack CancellationIBM·Filed 2009·Application pending·0 cites
- 1242US7203518B2Method and apparatus for simplified data dispensation to and from digital systemsIBM·Filed 2001·Granted Apr 10, 2007·0 cites·8 claims
- 1342US2008178133A1Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering BuffersKUANG JENTE BENEDICT·Filed 2007·Application pending·0 cites
- 1441US2009024975A1Systems, methods and computer products for traversing design hierarchy using a scroll mechanismIBM·Filed 2007·Application pending·0 cites
- 1541US2008266246A1Traversing graphical layers using a scrolling mechanism in a physical design environmentIBM·Filed 2007·Application pending·0 cites
- 1638US2008082300A1Design Structure for a Metal Fill Region of a Semiconductor ChipIBM·Filed 2007·Application pending·0 cites
- 1735US6084810ADynamic logic circuit with bitline repeater circuitIBM·Filed 1999·Granted Jul 4, 2000·4 cites·8 claims
- 1831US6266800B1System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determinationIBM·Filed 1999·Granted Jul 24, 2001·1 cites·16 claims
- 1930US5973971ADevice and method for verifying independent reads and writes in a memory arrayIBM·Filed 1998·Granted Oct 26, 1999·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →