Inventor · disambiguated record
Satoru Sueki
Also filed as: SUEKI SATORU
12 granted patents·372 citations·filing 2008–2011
92Inventor score
Technology areasH10W
Top patents by PatentIndex Score
12 records- 0198US7863095B2Method of manufacturing layered chip packageHEADWAY TECHNOLOGIES INC·Filed 2010·Granted Jan 4, 2011·233 cites·12 claims
- 0293US7557439B1Layered chip package that implements memory deviceTDK CORP·Filed 2008·Granted Jul 7, 2009·31 cites·12 claims
- 0391US7767494B2Method of manufacturing layered chip packageHEADWAY TECHNOLOGIES INC·Filed 2008·Granted Aug 3, 2010·24 cites·10 claims
- 0491US7745259B2Layered chip package and method of manufacturing sameHEADWAY TECHNOLOGIES INC·Filed 2008·Granted Jun 29, 2010·24 cites·6 claims
- 0589US7968374B2Layered chip package with wiring on the side surfacesHEADWAY TECHNOLOGIES INC·Filed 2009·Granted Jun 28, 2011·17 cites·18 claims
- 0683US8154116B2Layered chip package with heat sinkSASAKI YOSHITAKA·Filed 2008·Granted Apr 10, 2012·11 cites·18 claims
- 0783US7868442B2Layered chip package and method of manufacturing sameHEADWAY TECHNOLOGIES INC·Filed 2008·Granted Jan 11, 2011·10 cites·2 claims
- 0881US8134229B2Layered chip packageSASAKI YOSHITAKA·Filed 2010·Granted Mar 13, 2012·5 cites·3 claims
- 0980US7964976B2Layered chip package and method of manufacturing sameHEADWAY TECHNOLOGIES INC·Filed 2008·Granted Jun 21, 2011·8 cites·3 claims
- 1076US7846772B2Layered chip package and method of manufacturing sameHEADWAY TECHNOLOGIES INC·Filed 2008·Granted Dec 7, 2010·6 cites·15 claims
- 1173US8324741B2Layered chip package with wiring on the side surfacesSASAKI YOSHITAKA·Filed 2011·Granted Dec 4, 2012·3 cites·11 claims
- 1247US8513034B2Method of manufacturing layered chip packageSASAKI YOSHITAKA·Filed 2011·Granted Aug 20, 2013·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →