Inventor · disambiguated record
Satoru Tagaya
Also filed as: TAGAYA SATORU
2 granted patents·9 pending applications·0 citations·filing 2012–2025
23Inventor score
Top patents by PatentIndex Score
11 records- 0162US2025335328A1Telemetry management in routing architecturesOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0262US2025348600A1Hardware enforced data isolationOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0361US2025355781A1Telemetry data collection in chiplet processor architectureOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0461US2025342136A1Chiplet composabilityOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0560US2025335578A1Multi-chiplet trusted execution environment (tee)OPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0658US2025337589A1Hardware assisted artificial intelligence model attestationOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0757US2025252040A1Methods and apparatus to execute memory access formulas in memory chipletsOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0855US2025258772A1Methods and apparatus to facilitate use of dynamic coherency models for memory objectsOPENCHIP & SOFTWARE TECH S L·Filed 2025·Application pending·0 cites
- 0934US9424032B2List vector processing apparatus, list vector processing method, storage medium, compiler, and information processing apparatusNEC CORP·Filed 2014·Granted Aug 23, 2016·0 cites·11 claims
- 1025US9081673B2Microprocessor and memory access methodTAGAYA SATORU·Filed 2012·Granted Jul 14, 2015·0 cites·10 claims
- 1123US2017068542A1Processor and store instruction conversion methodNEC CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →