Inventor · disambiguated record
Sagar Upadhyay
Also filed as: UPADHYAY SAGAR
14 granted patents·6 pending applications·7 citations·filing 2017–2024
84Inventor score
Top patents by PatentIndex Score
20 records- 0183US11056203B1Boosted bitlines for storage cell programmed state verification in a memory arrayINTEL CORP·Filed 2020·Granted Jul 6, 2021·2 cites·24 claims
- 0280US10276252B2Data storage device with operation based on temperature differenceINTEL CORP·Filed 2017·Granted Apr 30, 2019·5 cites·22 claims
- 0371US12488817B2Enhanced IO interface for plc program and program-suspend-resume operationsIntel NDTM US LLC·Filed 2023·Granted Dec 2, 2025·0 cites·20 claims
- 0467US12254933B2Smart prologue for nonvolatile memory program operationIntel NDTM US LLC·Filed 2024·Granted Mar 18, 2025·0 cites·20 claims
- 0562US12394497B2Efficient bitline stabilization for program inhibit in NAND arraysIntel NDTM US LLC·Filed 2023·Granted Aug 19, 2025·0 cites·18 claims
- 0660US12189955B2Skip program verify for dynamic start voltage samplingIntel NDTM US LLC·Filed 2022·Granted Jan 7, 2025·0 cites·20 claims
- 0755US12046303B2Smart prologue for nonvolatile memory program operationIntel NDTM US LLC·Filed 2020·Granted Jul 23, 2024·0 cites·14 claims
- 0852US12315567B2Grouped global wordline driver with shared bias schemeIntel NDTM US LLC·Filed 2021·Granted May 27, 2025·0 cites·16 claims
- 0951US10956081B2Method, system, and apparatus for multi-tiered progressive memory program operation suspend and resumeINTEL CORP·Filed 2019·Granted Mar 23, 2021·0 cites·20 claims
- 1049US2023376215A1Multi-deck nand memory with hybrid deck slcIntel NDTM US LLC·Filed 2022·Application pending·0 cites
- 1149US2024136002A1Simultaneous statistical multi-subblock verify for nand memoriesIntel NDTM US LLC·Filed 2023·Application pending·0 cites
- 1248US12230334B2Dynamic program cachingIntel NDTM US LLC·Filed 2022·Granted Feb 18, 2025·0 cites·21 claims
- 1344US11923016B2Progressive program suspend resumeINTEL CORP·Filed 2020·Granted Mar 5, 2024·0 cites·18 claims
- 1444US2024071532A1Fast and efficient verify recovery and array discharge for 3d nand memory arraysIntel NDTM US LLC·Filed 2023·Application pending·0 cites
- 1543US12211563B2Dynamic gate steps for last-level programming to improve write performanceINTEL CORP·Filed 2021·Granted Jan 28, 2025·0 cites·20 claims
- 1643US12154627B2Block list management for wordline start voltageINTEL CORP·Filed 2021·Granted Nov 26, 2024·0 cites·20 claims
- 1742US11139036B2Using variable voltages to discharge electrons from a memory array during verify recovery operationsINTEL CORP·Filed 2020·Granted Oct 5, 2021·0 cites·22 claims
- 1840US2022262431A1Detected threshold voltage state distribution of first and second pass programed memory pagesIntel NDTM US LLC·Filed 2022·Application pending·0 cites
- 1937US2023138471A1Dynamic negative charge pump for non-volatile memoryIntel NDTM US LLC·Filed 2022·Application pending·0 cites
- 2034US2019006016A1Method, system, and apparatus for detecting failure of programming of a memory deviceINTEL CORP·Filed 2017·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Sagar Upadhyay files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →