Inventor · disambiguated record
Scott A. Kreps
Also filed as: KREPS SCOTT A
27 granted patents·11 pending applications·3,113 citations·filing 2003–2018
98Inventor score
Top patents by PatentIndex Score
38 records- 0199US7435988B2Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelMEARS TECHNOLOGIES INC·Filed 2005·Granted Oct 14, 2008·110 cites·37 claims
- 0299US7303948B2Semiconductor device including MOSFET having band-engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2005·Granted Dec 4, 2007·110 cites·11 claims
- 0399US7265002B2Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelRJ MEARS LLC·Filed 2005·Granted Sep 4, 2007·114 cites·39 claims
- 0498US10741436B2Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interfaceATOMERA INC·Filed 2018·Granted Aug 11, 2020·30 cites·23 claims
- 0598US7659539B2Semiconductor device including a floating gate memory cell with a superlattice channelMEARS TECHNOLOGIES INC·Filed 2006·Granted Feb 9, 2010·118 cites·17 claims
- 0698US7612366B2Semiconductor device including a strained superlattice layer above a stress layerMEARS TECHNOLOGIES INC·Filed 2006·Granted Nov 3, 2009·120 cites·33 claims
- 0798US7598515B2Semiconductor device including a strained superlattice and overlying stress layer and related methodsMEARS TECHNOLOGIES INC·Filed 2006·Granted Oct 6, 2009·115 cites·15 claims
- 0898US7586116B2Semiconductor device having a semiconductor-on-insulator configuration and a superlatticeMEARS TECHNOLOGIES INC·Filed 2006·Granted Sep 8, 2009·111 cites·23 claims
- 0998US7531828B2Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regionsMEARS TECHNOLOGIES INC·Filed 2006·Granted May 12, 2009·118 cites·27 claims
- 1098US7446002B2Method for making a semiconductor device comprising a superlattice dielectric interface layerMEARS TECHNOLOGIES INC·Filed 2005·Granted Nov 4, 2008·120 cites·21 claims
- 1198US7436026B2Semiconductor device comprising a superlattice channel vertically stepped above source and drain regionsMEARS TECHNOLOGIES INC·Filed 2004·Granted Oct 14, 2008·113 cites·45 claims
- 1298US7288457B2Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regionsRJ MEARS LLC·Filed 2004·Granted Oct 30, 2007·111 cites·46 claims
- 1398US7279701B2Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regionsRJ MEARS LLC·Filed 2004·Granted Oct 9, 2007·119 cites·46 claims
- 1498US7202494B2FINFET including a superlatticeRJ MEARS LLC·Filed 2006·Granted Apr 10, 2007·140 cites·23 claims
- 1598US7153763B2Method for making a semiconductor device including band-engineered superlattice using intermediate annealingRJ MEARS LLC·Filed 2005·Granted Dec 26, 2006·119 cites·31 claims
- 1698US7071119B2Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Jul 4, 2006·112 cites·26 claims
- 1798US7034329B2Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Apr 25, 2006·114 cites·26 claims
- 1898US7018900B2Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regionsRJ MEARS LLC·Filed 2004·Granted Mar 28, 2006·114 cites·48 claims
- 1998US6958486B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 25, 2005·114 cites·71 claims
- 2098US6952018B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 4, 2005·112 cites·26 claims
- 2198US6927413B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Aug 9, 2005·113 cites·26 claims
- 2298US6897472B2Semiconductor device including MOSFET having band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted May 24, 2005·153 cites·71 claims
- 2398US6891188B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted May 10, 2005·123 cites·36 claims
- 2498US6830964B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Dec 14, 2004·136 cites·76 claims
- 2597US7033437B2Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Apr 25, 2006·110 cites·28 claims
- 2697US6833294B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Dec 21, 2004·127 cites·28 claims
- 2795US6878576B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Apr 12, 2005·117 cites·36 claims
- 2840US2006292765A1Method for Making a FINFET Including a SuperlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2940US2006263980A1Method for making a semiconductor device including a floating gate memory cell with a superlattice channelRJ MEARS LLC STATE OF INC DELA·Filed 2006·Application pending·0 cites
- 3040US2007010040A1Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress LayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3140US2006243964A1Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3240US2007012910A1Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3340US2007020860A1Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related MethodsRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3440US2007015344A1Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress RegionsRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3540US2007020833A1Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3639US2005279991A1Semiconductor device including a superlattice having at least one group of substantially undoped layersRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 3739US2005282330A1Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layersRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 3838US2006011905A1Semiconductor device comprising a superlattice dielectric interface layerRJ MEARS LLC·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →