Inventor · disambiguated record
Scott Thompson
Also filed as: THOMPSON SCOTT · THOMPSON SCOTT E · THOMPSON SCOTT EMMET
15 granted patents·1 pending application·422 citations·filing 1995–2010
94Inventor score
Top patents by PatentIndex Score
16 records- 0194US6624032B2Structure and process flow for fabrication of dual gate floating body integrated MOS transistorsINTEL CORP·Filed 2002·Granted Sep 23, 2003·85 cites·13 claims
- 0288US6392271B1Structure and process flow for fabrication of dual gate floating body integrated MOS transistorsINTEL CORP·Filed 1999·Granted May 21, 2002·64 cites·7 claims
- 0384US6020244AChannel dopant implantation with automatic compensation for variations in critical dimensionINTEL CORP·Filed 1996·Granted Feb 1, 2000·75 cites·10 claims
- 0479US6800887B1Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2003·Granted Oct 5, 2004·17 cites·5 claims
- 0578US5976939ALow damage doping technique for self-aligned source and drain regionsINTEL CORP·Filed 1995·Granted Nov 2, 1999·54 cites·4 claims
- 0676US7312485B2CMOS fabrication process utilizing special transistor orientationINTEL CORP·Filed 2000·Granted Dec 25, 2007·21 cites·11 claims
- 0773US7226824B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Jun 5, 2007·11 cites·11 claims
- 0870US7888710B2CMOS fabrication process utilizing special transistor orientationINTEL CORP·Filed 2007·Granted Feb 15, 2011·3 cites·12 claims
- 0965US7187057B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Mar 6, 2007·7 cites·12 claims
- 1065US6515351B2Integrated circuit with borderless contactsINTEL CORP·Filed 2001·Granted Feb 4, 2003·11 cites·5 claims
- 1164US6228777B1Integrated circuit with borderless contactsINTEL CORP·Filed 1999·Granted May 8, 2001·26 cites·10 claims
- 1258US5877072AProcess for forming doped regions from solid phase diffusion sourceINTEL CORP·Filed 1997·Granted Mar 2, 1999·22 cites·20 claims
- 1354US7723720B2Methods and articles incorporating local stress for performance improvement of strained semiconductor devicesUNIV FLORIDA·Filed 2005·Granted May 25, 2010·2 cites·14 claims
- 1450US6294823B1Integrated circuit with insulating spacers separating borderless contacts from the wellINTEL CORP·Filed 1999·Granted Sep 25, 2001·16 cites·9 claims
- 1540US5874344ATwo step source/drain anneal to prevent dopant evaporationINTEL CORP·Filed 1996·Granted Feb 23, 1999·8 cites·7 claims
- 1636US2012199812A1Strain tunable silicon and germanium nanowire optoelectronic devicesBAYKAN MEHMET ONUR·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →