Inventor · disambiguated record
Sébastien Barasinski
Also filed as: BARASINSKI SEBASTIEN
9 granted patents·22 citations·filing 2005–2010
82Inventor score
Top patents by PatentIndex Score
9 records- 0176US7209383B2Magnetic random access memory array having bit/word lines for shared write select and read operationsST MICROELECTRONICS INC·Filed 2005·Granted Apr 24, 2007·10 cites·30 claims
- 0266US7751229B2SRAM memory device with improved write operation and method thereofST MICROELECTRONICS SA·Filed 2006·Granted Jul 6, 2010·5 cites·17 claims
- 0362US7795917B2High-speed buffer circuit, system and methodST MICROELECTRONICS SA·Filed 2008·Granted Sep 14, 2010·4 cites·26 claims
- 0459US8044728B2Circuit and method for measuring the performance parameters of transistorsST MICROELECTRONICS SA·Filed 2009·Granted Oct 25, 2011·1 cites·10 claims
- 0553US8335121B2Method for implementing an SRAM memory information storage deviceDRAY CYRILLE·Filed 2010·Granted Dec 18, 2012·1 cites·17 claims
- 0646US7372728B2Magnetic random access memory array having bit/word lines for shared write select and read operationsST MICROELECTRONICS INC·Filed 2007·Granted May 13, 2008·1 cites·17 claims
- 0737US7755927B2Memory device of SRAM typeST MICROELECTRONICS SA·Filed 2007·Granted Jul 13, 2010·0 cites·23 claims
- 0836US7139212B2Memory architecture with segmented writing linesST MICROELECTRONICS SA·Filed 2005·Granted Nov 21, 2006·0 cites·26 claims
- 0935US7545686B2Device for setting up a write current in an MRAM type memory and memory comprisingST MICROELECTRONICS SA·Filed 2005·Granted Jun 9, 2009·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →