Inventor · disambiguated record
Sergei Drizlikh
Also filed as: DRIZLIKH SERGEI
10 granted patents·1 pending application·48 citations·filing 2002–2015
86Inventor score
Top patents by PatentIndex Score
11 records- 0179US9418856B2Methods of forming titanium-aluminum layers for gate electrodes and related semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Aug 16, 2016·4 cites·17 claims
- 0278US7229908B1System and method for manufacturing an out of plane integrated circuit inductorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 12, 2007·26 cites·20 claims
- 0364US8481142B1System and method for monitoring chloride content and concentration induced by a metal etch processBUDRI THANAS·Filed 2005·Granted Jul 9, 2013·3 cites·20 claims
- 0460US7645657B2MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradationNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jan 12, 2010·1 cites·20 claims
- 0558US7531896B1Semiconductor device having a minimal via resistance created by applying a nitrogen plasma to a titanium via linerNAT SEMICONDUCTOR CORP·Filed 2006·Granted May 12, 2009·1 cites·20 claims
- 0653US7247544B1High Q inductor integrationNAT SEMICONDUCTOR CORP·Filed 2002·Granted Jul 24, 2007·6 cites·12 claims
- 0752US7504340B1System and method for providing contact etch selectivity using RIE lag dependence on contact aspect ratioNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 17, 2009·4 cites·16 claims
- 0843US7915093B1System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug processNAT SEMICONDUCTOR CORP·Filed 2006·Granted Mar 29, 2011·0 cites·20 claims
- 0940US8471369B1Method and apparatus for reducing plasma process induced damage in integrated circuitsMCCULLOH HEATHER·Filed 2004·Granted Jun 25, 2013·3 cites·4 claims
- 1040US7101787B1System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner depositionNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 5, 2006·0 cites·20 claims
- 1139US2011221031A1System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug processNAT SEMICONDUCTOR CORP·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →