Inventor · disambiguated record
Sebastian Ehrenreich
Also filed as: EHRENREICH SEBASTIAN
17 granted patents·4 pending applications·122 citations·filing 2002–2025
93Inventor score
Top patents by PatentIndex Score
21 records- 0189US7414904B2Method for evaluating storage cell design using a wordline timing and cell access detection circuitIBM·Filed 2006·Granted Aug 19, 2008·22 cites·2 claims
- 0288US7813163B2Single-ended read and differential write schemeIBM·Filed 2008·Granted Oct 12, 2010·20 cites·11 claims
- 0385US7808856B2Method to reduce leakage of a SRAM-arrayIBM·Filed 2008·Granted Oct 5, 2010·16 cites·5 claims
- 0476US8363487B2Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuitIBM·Filed 2010·Granted Jan 29, 2013·6 cites·23 claims
- 0573US6937847B2Integrated RF signal level detector usable for automatic power level controlADVANCED MICRO DEVICES INC·Filed 2002·Granted Aug 30, 2005·21 cites·26 claims
- 0671US7636254B2Wordline booster circuit and method of operating a wordline booster circuitIBM·Filed 2007·Granted Dec 22, 2009·6 cites·15 claims
- 0770US8476966B2On-die voltage regulation using p-FET header devices with a feedback control loopBUECHNER THOMAS·Filed 2011·Granted Jul 2, 2013·4 cites·19 claims
- 0868US7336115B2Redundancy in signal distribution treesIBM·Filed 2006·Granted Feb 26, 2008·3 cites·6 claims
- 0967US7755408B2Redundancy in signal distribution treesIBM·Filed 2007·Granted Jul 13, 2010·4 cites·12 claims
- 1067US7626851B2Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuitIBM·Filed 2007·Granted Dec 1, 2009·6 cites·2 claims
- 1164US2025283903A1Method for operating an in-vitro-diagnostics laboratory system and in-vitro-diagnostics laboratory systemROCHE DIAGNOSTICS OPERATIONS INC·Filed 2025·Application pending·0 cites
- 1256US7675794B2Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuitIBM·Filed 2007·Granted Mar 9, 2010·3 cites·3 claims
- 1355US8513663B2Signal repowering chip for 3-dimensional integrated circuitBUEHLER MARKUS·Filed 2010·Granted Aug 20, 2013·1 cites·5 claims
- 1454US2008048729A1Comparator Circuit and Method for Operating a Comparator CircuitIBM·Filed 2007·Application pending·0 cites
- 1553US7921388B2Wordline booster design structure and method of operating a wordine booster circuitIBM·Filed 2007·Granted Apr 5, 2011·2 cites·10 claims
- 1652US7558138B1Bypass circuit for memory arraysIBM·Filed 2008·Granted Jul 7, 2009·4 cites·1 claims
- 1747US7532869B2Automatic power level control circuit for a transceiver deviceADVANCED MICRO DEVICES INC·Filed 2002·Granted May 12, 2009·4 cites·17 claims
- 1844US2007165343A1Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a CircuitBAROWSKI HARRY·Filed 2006·Application pending·0 cites
- 1938US2008178129A1Comparator Circuit and Method for Operating a Comparator CircuitIBM·Filed 2007·Application pending·0 cites
- 2036US7564739B2Storage cell design evaluation circuit including a wordline timing and cell access detection circuitIBM·Filed 2008·Granted Jul 21, 2009·0 cites·17 claims
- 2135US7535750B2Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cellsIBM·Filed 2007·Granted May 19, 2009·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →