Inventor · disambiguated record
Sean Gibb
Also filed as: GIBB SEAN · GIBB SEAN G · GIBB SEAN GREGORY
18 granted patents·3 pending applications·194 citations·filing 2004–2023
94Inventor score
Files withPMC SIERRA US INC8EIDETIC COMMUNICATIONS INC6CYGNUS COMM CANADA CO2GIBB SEAN G1GRAUMANN PETER1
Top patents by PatentIndex Score
21 records- 0196US9564922B1Error correction code decoder with stochastic floor mitigationPMC-SIERRA US INC·Filed 2015·Granted Feb 7, 2017·19 cites·21 claims
- 0296US9170876B1Method and system for decoding encoded data stored in a non-volatile memoryPMC SIERRA US INC·Filed 2013·Granted Oct 27, 2015·39 cites·19 claims
- 0395US9325347B1Forward error correction decoder and method thereforPMC SIERRA US INC·Filed 2014·Granted Apr 26, 2016·21 cites·17 claims
- 0494US9432053B1High speed LDPC decoderMICROSEMI STORAGE SOLUTIONS (U S ) INC·Filed 2014·Granted Aug 30, 2016·29 cites·26 claims
- 0593US9602133B1System and method for boost floor mitigationPMC-SIERRA US INC·Filed 2015·Granted Mar 21, 2017·13 cites·15 claims
- 0691US9564921B1Method and system for forward error correction decoding based on a revised error channel estimatePMC-SIERRA US INC·Filed 2015·Granted Feb 7, 2017·11 cites·19 claims
- 0787US9793924B1Method and system for estimating an expectation of forward error correction decoder convergenceMICROSEMI SOLUTIONS (U S ) INC·Filed 2015·Granted Oct 17, 2017·6 cites·20 claims
- 0886US9467172B1Forward error correction decoder and method thereforPMC-SIERRA US INC·Filed 2016·Granted Oct 11, 2016·6 cites·18 claims
- 0985US9473175B1Forward error correction decoder systemPMC-SIERRA US INC·Filed 2015·Granted Oct 18, 2016·9 cites·15 claims
- 1082US8938037B1High speed gain and phase recovery in presence of phase noisePMC SIERRA US INC·Filed 2013·Granted Jan 20, 2015·11 cites·3 claims
- 1178US8631309B2Forward error correction with extended effective block sizeGRAUMANN PETER·Filed 2012·Granted Jan 14, 2014·7 cites·56 claims
- 1272US10996892B2Apparatus and method for controlling data accelerationEIDETIC COMMUNICATIONS INC·Filed 2018·Granted May 4, 2021·2 cites·20 claims
- 1363US7428564B2Pipelined FFT processor with memory address interleavingGIBB SEAN G·Filed 2004·Granted Sep 23, 2008·13 cites·25 claims
- 1458US7415584B2Interleaving input sequences to memoryCYGNUS COMM CANADA CO·Filed 2004·Granted Aug 19, 2008·8 cites·29 claims
- 1557US11804852B2System and method for mitigating effects of hash collisions in hardware data compressionEIDETIC COMMUNICATIONS INC·Filed 2021·Granted Oct 31, 2023·0 cites·19 claims
- 1655US12222872B1Method and apparatus for generating a histogramEIDETIC COMMUNICATIONS INC·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 1747US11687365B2Method and apparatus for controlling a computational storage processorEIDETIC COMMUNICATIONS INC·Filed 2020·Granted Jun 27, 2023·0 cites·20 claims
- 1847US2008288569A1Pipelined fft processor with memory address interleavingCYGNUS COMM CANADA CO·Filed 2008·Application pending·0 cites
- 1946US12222892B2Routing data between processing units indentified by a sequentially ordered list of a packet prefixEIDETIC COMMUNICATIONS INC·Filed 2022·Granted Feb 11, 2025·0 cites·14 claims
- 2044US2019163364A1System and method for tcp offload for nvme over tcp-ipEIDETIC COMMUNICATIONS INC·Filed 2018·Application pending·0 cites
- 2143US2005015420A1Recoded radix-2 pipeline FFT processorFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →