Inventor · disambiguated record
Sergey Gribok
Also filed as: GRIBOK SERGEY · GRIBOK SERGEY V · GRIBOK SERGEY VLADIMIROVICH
24 granted patents·13 pending applications·111 citations·filing 2004–2025
93Inventor score
Top patents by PatentIndex Score
37 records- 0197US10922471B2High performance regularized network-on-chip architectureINTEL CORP·Filed 2019·Granted Feb 16, 2021·19 cites·20 claims
- 0293US8629548B1Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic nodeEASIC CORP·Filed 2012·Granted Jan 14, 2014·56 cites·20 claims
- 0388US10732932B2Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extensionINTEL CORP·Filed 2018·Granted Aug 4, 2020·6 cites·22 claims
- 0486US11467804B2Geometric synthesisINTEL CORP·Filed 2019·Granted Oct 11, 2022·4 cites·20 claims
- 0579US10715144B2Logic circuits with augmented arithmetic densitiesINTEL CORP·Filed 2019·Granted Jul 14, 2020·2 cites·20 claims
- 0677US8735857B2Via-configurable high-performance logic block architectureANDREEV ALEXANDER·Filed 2011·Granted May 27, 2014·5 cites·14 claims
- 0777US8436700B2MEMS-based switchingSCHMIT HERMAN·Filed 2009·Granted May 7, 2013·8 cites·21 claims
- 0873US8957398B2Via-configurable high-performance logic block involving transistor chainsEASIC CORP·Filed 2012·Granted Feb 17, 2015·4 cites·14 claims
- 0973US2025199762A1Machine learning training architecture for programmable devicesALTERA CORP·Filed 2025·Application pending·0 cites
- 1071US10102892B1RAM-based shift register with embedded addressingINTEL CORP·Filed 2017·Granted Oct 16, 2018·3 cites·17 claims
- 1167US2022107783A1Machine learning training architecture for programmable devicesINTEL CORP·Filed 2021·Application pending·0 cites
- 1263US11556692B2High performance regularized network-on-chip architectureINTEL CORP·Filed 2020·Granted Jan 17, 2023·0 cites·20 claims
- 1361US11080019B2Method and apparatus for performing synthesis for field programmable gate array embedded feature placementINTEL CORP·Filed 2018·Granted Aug 3, 2021·0 cites·23 claims
- 1459US2025013431A1Modular Multipliers using Hybrid Reduction TechniquesALTERA CORP·Filed 2024·Application pending·0 cites
- 1558US11210063B2Machine learning training architecture for programmable devicesINTEL CORP·Filed 2019·Granted Dec 28, 2021·0 cites·20 claims
- 1657US11334318B2Prefix network-directed additionINTEL CORP·Filed 2018·Granted May 17, 2022·0 cites·20 claims
- 1755US10867090B2Method and apparatus for implementing an application aware system on a programmable logic deviceINTEL CORP·Filed 2019·Granted Dec 15, 2020·0 cites·24 claims
- 1854US10871946B2Methods for using a multiplier to support multiple sub-multiplication operationsINTEL CORP·Filed 2018·Granted Dec 22, 2020·0 cites·24 claims
- 1953US2023273770A1Iterative Multiplicative Reduction CircuitINTEL CORP·Filed 2023·Application pending·0 cites
- 2052US10790829B2Logic circuits with simultaneous dual function capabilityINTEL CORP·Filed 2018·Granted Sep 29, 2020·0 cites·19 claims
- 2152US7430694B2Memory BISR architecture for a sliceLSI CORP·Filed 2005·Granted Sep 30, 2008·2 cites·20 claims
- 2252US2023239136A1Pipelined Galois Counter Mode Hash CircuitGRIBOK SERGEY VLADIMIROVICH·Filed 2023·Application pending·0 cites
- 2352US2023018414A1Retiming and Overclocking of Large CircuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 2451US2023026331A1High Performance Systems And Methods For Modular MultiplicationINTEL CORP·Filed 2022·Application pending·0 cites
- 2547US2023027064A1Power Savings by Register Insertion in Large Combinational CircuitsLANGHAMMER MARTIN·Filed 2022·Application pending·0 cites
- 2646US7546505B2Built in self test transport controller architectureLSI CORP·Filed 2006·Granted Jun 9, 2009·1 cites·4 claims
- 2746US2009287980A1Computational Architecture for Soft DecodingLSI CORP·Filed 2008·Application pending·0 cites
- 2845US11436399B2Method and apparatus for performing multiplier regularizationINTEL CORP·Filed 2018·Granted Sep 6, 2022·0 cites·24 claims
- 2943US11016733B2Continuous carry-chain packingINTEL CORP·Filed 2018·Granted May 25, 2021·0 cites·20 claims
- 3042US9239704B2Variable node processing unitAVAGO TECHNOLOGIES GENERAL IP·Filed 2013·Granted Jan 19, 2016·0 cites·12 claims
- 3140US2011173510A1Parallel LDPC DecoderLSI CORP·Filed 2011·Application pending·0 cites
- 3240US2011099454A1Low Complexity LDPC Encoding AlgorithmLSI CORP·Filed 2011·Application pending·0 cites
- 3338US2012278372A1Cryptographic Random Number Generator Using Finite Field OperationsGRIBOK SERGEY·Filed 2012·Application pending·0 cites
- 3437US7283385B2RRAM communication systemLSI CORP·Filed 2004·Granted Oct 16, 2007·1 cites·26 claims
- 3535US7328382B2Memory BISR controller architectureLSI LOGIC CORP·Filed 2005·Granted Feb 5, 2008·0 cites·20 claims
- 3633US7308633B2Master controller architectureLSI CORP·Filed 2004·Granted Dec 11, 2007·0 cites·1 claims
- 3729US2014103985A1Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed InterfaceEASIC CORP·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →