Inventor · disambiguated record
Seiki Ogura
Also filed as: OGURA SEIKI · OGURA SEIKI O
130 granted patents·2 pending applications·6,156 citations·filing 1975–2014
99Inventor score
Files withIBM45HALO LSI INC40MATSUSHITA ELECTRIC INDUSTRIAL CO LTD20HALO LSI DESIGN & DEVICE TECH11HALO LSI DEVICE & DESIGN TECHN3
Top patents by PatentIndex Score
132 records- 0199US6255166B1Nonvolatile memory cell, method of programming the same and nonvolatile memory arrayHALO LSI DESIGN & DEVICE TECH·Filed 1999·Granted Jul 3, 2001·454 cites·40 claims
- 0299US5528062AHigh-density DRAM structure on soiIBM·Filed 1992·Granted Jun 18, 1996·307 cites·20 claims
- 0399US5466625AMethod of making a high-density DRAM structure on SOIIBM·Filed 1994·Granted Nov 14, 1995·240 cites·3 claims
- 0498US6388293B1Nonvolatile memory cell, operating method of the same and nonvolatile memory arrayHALO LSI DESIGN & DEVICE TECH·Filed 2000·Granted May 14, 2002·220 cites·33 claims
- 0598US6133098AProcess for making and programming and operating a dual-bit multi-level ballistic flash memoryHALO LSI DESIGN & DEVICE TECH·Filed 1999·Granted Oct 17, 2000·251 cites·63 claims
- 0698US5780341ALow voltage EEPROM/NVRAM transistors and making methodHALO LSI DESIGN & DEVICE TECH·Filed 1996·Granted Jul 14, 1998·233 cites·32 claims
- 0797US6670240B2Twin NAND device structure, array operations and fabrication methodHALO LSI INC·Filed 2002·Granted Dec 30, 2003·124 cites·38 claims
- 0897US6531350B2Twin MONOS cell fabrication method and array organizationHALO INC·Filed 2001·Granted Mar 11, 2003·142 cites·54 claims
- 0997US6177318B1Integration method for sidewall split gate monos transistorHALO LSI DESIGN & DEVICE TECH·Filed 1999·Granted Jan 23, 2001·198 cites·24 claims
- 1097US4648937AMethod of preventing asymmetric etching of lines in sub-micrometer range sidewall images transferIBM·Filed 1985·Granted Mar 10, 1987·348 cites·18 claims
- 1197US4366613AMethod of fabricating an MOS dynamic RAM with lightly doped drainIBM·Filed 1980·Granted Jan 4, 1983·115 cites·13 claims
- 1296US6399441B1Nonvolatile memory cell, method of programming the same and nonvolatile memory arrayHALO LSI DEVICE & DESIGN TECHN·Filed 2001·Granted Jun 4, 2002·122 cites·52 claims
- 1396US6248633B1Process for making and programming and operating a dual-bit multi-level ballistic MONOS memoryHALO LSI DESIGN & DEVICE TECH·Filed 1999·Granted Jun 19, 2001·347 cites·64 claims
- 1495US4671851AMethod for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing techniqueIBM·Filed 1985·Granted Jun 9, 1987·189 cites·15 claims
- 1592US4868135AMethod for manufacturing a Bi-CMOS deviceIBM·Filed 1988·Granted Sep 19, 1989·77 cites·21 claims
- 1691US6707079B2Twin MONOS cell fabrication method and array organizationHALO LSI INC·Filed 2003·Granted Mar 16, 2004·83 cites·19 claims
- 1791US6180461B1Double sidewall short channel split gate flash memoryHALO LSI DESIGN & DEVICE TECH·Filed 1998·Granted Jan 30, 2001·64 cites·10 claims
- 1891US6107141AFlash EEPROMIBM·Filed 1998·Granted Aug 22, 2000·83 cites·4 claims
- 1991US5516721AIsolation structure using liquid phase oxide depositionIBM·Filed 1995·Granted May 14, 1996·126 cites·13 claims
- 2091US4636822AGaAs short channel lightly doped drain MESFET structure and fabricationIBM·Filed 1984·Granted Jan 13, 1987·63 cites·14 claims
- 2190US6477088B2Usage of word voltage assistance in twin MONOS cell during program and eraseHALO LSI DESIGN & DEVICE TECH·Filed 2001·Granted Nov 5, 2002·56 cites·32 claims
- 2290US6157058ALow voltage EEPROM/NVRAM transistors and making methodHALO LSI DESIGN DEVICE TECHNOL·Filed 1998·Granted Dec 5, 2000·93 cites·17 claims
- 2390US5910912AFlash EEPROM with dual-sidewall gateIBM·Filed 1992·Granted Jun 8, 1999·76 cites·6 claims
- 2489US6900098B1Twin insulator charge storage device operation and its fabrication methodHALO LSI INC·Filed 2003·Granted May 31, 2005·33 cites·37 claims
- 2589US6686632B2Dual-bit multi-level ballistic MONOS memoryNEW HALO INC·Filed 2001·Granted Feb 3, 2004·43 cites·21 claims
- 2689US6549463B2Fast program to program verify methodHALO LSI INC·Filed 2001·Granted Apr 15, 2003·31 cites·7 claims
- 2789US6459622B1Twin MONOS memory cell usage for wide programHALO LSI INC·Filed 2002·Granted Oct 1, 2002·50 cites·43 claims
- 2889US5376578AMethod of fabricating a semiconductor device with raised diffusions and isolationIBM·Filed 1993·Granted Dec 27, 1994·79 cites·19 claims
- 2988US7394703B2Twin insulator charge storage device operation and its fabrication methodHALO LSI INC·Filed 2006·Granted Jul 1, 2008·12 cites·1 claims
- 3088US6807105B2Fast program to program verify methodHALO LSI INC·Filed 2003·Granted Oct 19, 2004·27 cites·4 claims
- 3188US6366500B1Process for making and programming and operating a dual-bit multi-level ballistic flash memoryHALO LSI DEVICE & DESIGN TECHN·Filed 2000·Granted Apr 2, 2002·37 cites·45 claims
- 3287US7170132B2Twin insulator charge storage device operation and its fabrication methodHALO LSI INC·Filed 2005·Granted Jan 30, 2007·10 cites·11 claims
- 3387US6756271B1Simplified twin monos fabrication method with three extra masks to standard CMOSHALO LSI INC·Filed 2003·Granted Jun 29, 2004·64 cites·56 claims
- 3487US6538275B2Nonvolatile semiconductor memory device and method for fabricating the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Mar 25, 2003·39 cites·8 claims
- 3587US6380585B1Nonvolatile semiconductor device capable of increased electron injection efficiencyMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted Apr 30, 2002·37 cites·7 claims
- 3685US6759290B2Stitch and select implementation in twin MONOS arrayHALO LSI INC·Filed 2002·Granted Jul 6, 2004·31 cites·40 claims
- 3785US6359807B1Process for making and programming and operating a dual-bit multi-level ballistic flash memoryHALO LSI DEVICE & DESIGN TECHN·Filed 2000·Granted Mar 19, 2002·32 cites·3 claims
- 3885US6051860ANonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Apr 18, 2000·50 cites·7 claims
- 3984US7742336B2Trap-charge non-volatile switch connector for programmable logicGUMBO LOGIC INC·Filed 2007·Granted Jun 22, 2010·12 cites·4 claims
- 4084US6580116B2Double sidewall short channel split gate flash memoryHALO LSI INC·Filed 2000·Granted Jun 17, 2003·23 cites·14 claims
- 4184US6418062B1Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memoryHALO INC·Filed 2001·Granted Jul 9, 2002·38 cites·113 claims
- 4283US7006378B1Array architecture and operation methods for a nonvolatile memoryHALO LSI INC·Filed 2003·Granted Feb 28, 2006·31 cites·39 claims
- 4383US6825084B2Twin NAND device structure, array operations and fabrication methodHALO LSI INC·Filed 2003·Granted Nov 30, 2004·25 cites·13 claims
- 4483US6074914AIntegration method for sidewall split gate flash transistorHALO LSI DESIGN & DEVICE TECH·Filed 1998·Granted Jun 13, 2000·55 cites·20 claims
- 4582US7359250B2Twin insulator charge storage device operation and its fabrication methodHALO LSI INC·Filed 2006·Granted Apr 15, 2008·6 cites·8 claims
- 4682US6804149B2Nonvolatile memory cell, operating method of the same and nonvolatile memory arrayNEW HALO INC·Filed 2002·Granted Oct 12, 2004·33 cites·14 claims
- 4782US6542412B2Process for making and programming and operating a dual-bit multi-level ballistic flash memoryHALO LSI INC·Filed 2002·Granted Apr 1, 2003·26 cites·9 claims
- 4882US5622881APacking density for flash memoriesIBM·Filed 1994·Granted Apr 22, 1997·42 cites·10 claims
- 4982US5389559AMethod of forming integrated interconnect for very high density DRAMsIBM·Filed 1993·Granted Feb 14, 1995·46 cites·28 claims
- 5082US5241203AInverse T-gate FET transistor with lightly doped source and drain regionIBM·Filed 1992·Granted Aug 31, 1993·53 cites·2 claims
Showing the top 50 of 132 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Seiki Ogura files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →