Inventor · disambiguated record
Seyednaser Pourmousavian
Also filed as: POURMOUSAVIAN SEYEDNASER
7 granted patents·7 citations·filing 2016–2020
75Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD7
Top patents by PatentIndex Score
7 records- 0183US10171089B2PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applicationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 1, 2019·5 cites·17 claims
- 0274US10326454B2All-digital phase locked loop using switched capacitor voltage doublerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 18, 2019·2 cites·20 claims
- 0369US11177810B2All-digital phase locked loop using switched capacitor voltage doublerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 0464US11764211B2Device with a high efficiency voltage multiplierTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 19, 2023·0 cites·20 claims
- 0564US10862486B2All-digital phase locked loop using switched capacitor voltage doublerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 0655US10756083B2Device with a high efficiency voltage multiplierTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 25, 2020·0 cites·20 claims
- 0743US10277117B2Device with a voltage multiplierTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 30, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →