Inventor · disambiguated record
Sergey V. Rylov
Also filed as: RYLOV SERGEY · RYLOV SERGEY V · RYLOV SERGEY VLADIMIROVICH
33 granted patents·4 pending applications·490 citations·filing 1997–2023
97Inventor score
Top patents by PatentIndex Score
37 records- 0198US9571115B1Analog to digital converter with high precision offset calibrated integrating comparatorsIBM·Filed 2015·Granted Feb 14, 2017·44 cites·17 claims
- 0298US7486145B2Circuits and methods for implementing sub-integer-N frequency dividers using phase rotatorsIBM·Filed 2007·Granted Feb 3, 2009·55 cites·33 claims
- 0397US7365663B2Flux-quantizing superconducting analog to digital converter (ADC)HYPRES INC·Filed 2006·Granted Apr 29, 2008·55 cites·25 claims
- 0493US8704583B2Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifierBULZACCHELLI JOHN F·Filed 2012·Granted Apr 22, 2014·21 cites·21 claims
- 0592US9660660B1Analog to digital converter with high precision offset calibrated integrating comparatorsIBM·Filed 2016·Granted May 23, 2017·10 cites·6 claims
- 0692US5936458ASuperconducting analog amplifier circuitsHYPRES INC·Filed 1997·Granted Aug 10, 1999·84 cites·36 claims
- 0791US8564352B2High-resolution phase interpolatorsAGRAWAL ANKUR·Filed 2012·Granted Oct 22, 2013·9 cites·32 claims
- 0890US10680617B2Direct current powered clockless superconducting logic family using dynamic internal stateIBM·Filed 2018·Granted Jun 9, 2020·5 cites·13 claims
- 0989US9698968B2Phase interpolator calibrationIBM·Filed 2016·Granted Jul 4, 2017·8 cites·22 claims
- 1089US8558597B2High-resolution phase interpolatorsAGRAWAL ANKUR·Filed 2012·Granted Oct 15, 2013·7 cites·15 claims
- 1189US7468630B2Superconducting switching amplifierHYPRES INC·Filed 2007·Granted Dec 23, 2008·17 cites·28 claims
- 1287US7893861B2Time-to-digital based analog-to-digital converter architectureIBM·Filed 2009·Granted Feb 22, 2011·18 cites·25 claims
- 1387US6927611B2Semidigital delay-locked loop using an analog-based finite state machineIBM·Filed 2003·Granted Aug 9, 2005·38 cites·16 claims
- 1486US11115027B2Direct current powered clockless superconducting logic family using dynamic internal statesIBM·Filed 2020·Granted Sep 7, 2021·2 cites·19 claims
- 1585US8126045B2System and method for latency reduction in speculative decision feedback equalizersBULZACCHELLI JOHN FRANCIS·Filed 2008·Granted Feb 28, 2012·17 cites·20 claims
- 1685US7961025B2Current-mode phase rotator with partial phase switchingIBM·Filed 2009·Granted Jun 14, 2011·13 cites·28 claims
- 1784US8139700B2Dynamic quadrature clock correction for a phase rotator systemBEUKEMA TROY J·Filed 2009·Granted Mar 20, 2012·15 cites·24 claims
- 1883US9137070B2Apparatus and method for signal phase control in an integrated radio circuitBEUKEMA TROY JAMES·Filed 2008·Granted Sep 15, 2015·9 cites·35 claims
- 1983US8552783B2Programmable delay generator and cascaded interpolatorRYLOV SERGEY V·Filed 2011·Granted Oct 8, 2013·7 cites·16 claims
- 2081US7945805B2Architecture for a physical interface of a high speed front side busIBM·Filed 2007·Granted May 17, 2011·9 cites·17 claims
- 2177US9306729B2Phase interpolator calibrationIBM·Filed 2014·Granted Apr 5, 2016·4 cites·23 claims
- 2275US7602869B2Methods and apparatus for clock synchronization and data recovery in a receiverIBM·Filed 2005·Granted Oct 13, 2009·7 cites·20 claims
- 2374US7659763B2Conditioning input buffer for clock interpolationIBM·Filed 2008·Granted Feb 9, 2010·7 cites·19 claims
- 2469US8928384B2Programmable delay generator and cascaded interpolatorIBM·Filed 2013·Granted Jan 6, 2015·2 cites·9 claims
- 2567US7624297B2Architecture for a physical interface of a high speed front side busIBM·Filed 2006·Granted Nov 24, 2009·3 cites·17 claims
- 2665US7107301B2Method and apparatus for reducing latency in a digital signal processing deviceIBM·Filed 2002·Granted Sep 12, 2006·11 cites·20 claims
- 2762US8774228B2Timing recovery method and apparatus for an input/output bus with link redundancyBULZACCHELLI JOHN F·Filed 2011·Granted Jul 8, 2014·1 cites·23 claims
- 2861US9325542B2Power-scalable skew compensation in source-synchronous parallel interfacesGLOBALFOUNDRIES INC·Filed 2012·Granted Apr 26, 2016·1 cites·15 claims
- 2959US6903579B2Pipelined low-voltage current-mode logic with a switching stack height of oneIBM·Filed 2003·Granted Jun 7, 2005·8 cites·11 claims
- 3057US2023351234A1Effective synchronous gates for rapid single flux quantum logicIBM·Filed 2022·Application pending·0 cites
- 3154US12231123B2Metastability-free clockless single flux quantum logic circuitryIBM·Filed 2022·Granted Feb 18, 2025·0 cites·20 claims
- 3253US9253004B2Apparatus and method for signal phase control in an integrated radio circuitIBM·Filed 2015·Granted Feb 2, 2016·0 cites·35 claims
- 3349US2007160168A1Apparatus and method for signal phase control in an integrated radio circuitBEUKEMA TROY J·Filed 2006·Application pending·0 cites
- 3446US6859071B2Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logicIBM·Filed 2002·Granted Feb 22, 2005·3 cites·20 claims
- 3546US2025077804A1Power-efficient mixed-signal circuit including analog multiply and accumulate enginesIBM·Filed 2023·Application pending·0 cites
- 3644US11809837B2Integer matrix multiplication based on mixed signal circuitsIBM·Filed 2020·Granted Nov 7, 2023·0 cites·9 claims
- 3740US2009195286A1Phase shifting using asymmetric interpolator weightsRYLOV SERGEY VLADIMIROVICH·Filed 2008·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Sergey V. Rylov files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →