Inventor · disambiguated record
Sergey P. Scherbinin
Also filed as: SCHERBININ SERGEY P
6 granted patents·3 pending applications·2 citations·filing 2009–2016
67Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0154US9086873B2Methods and apparatus to compile instructions for a vector of instruction pointers processor architectureASTIGEYEVICH YEVGENIY M·Filed 2013·Granted Jul 21, 2015·2 cites·16 claims
- 0246US10235171B2Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processorINTEL CORP·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 0345US2010274972A1Systems, methods, and apparatuses for parallel computingBABAYAN BORIS·Filed 2009·Application pending·0 cites
- 0444US10241801B2Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·22 claims
- 0543US10241794B2Apparatus and methods to support counted loop exits in a multi-strand loop processorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 0643US10241789B2Method to do control speculation on loads in a high performance strand-based loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 0739US10430191B2Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruptionINTEL CORP·Filed 2015·Granted Oct 1, 2019·0 cites·20 claims
- 0836US2018181398A1Apparatus and methods of decomposing loops to improve performance and power efficiencyINTEL CORP·Filed 2016·Application pending·0 cites
- 0932US2017161075A1Increasing processor instruction window via seperating instructions according to criticalityINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →