Inventor · disambiguated record
Sean J. Treichler
Also filed as: TREICHLER SEAN · TREICHLER SEAN J · TREICHLER SEAN JEFFREY
56 granted patents·9 pending applications·833 citations·filing 2000–2024
98Inventor score
Top patents by PatentIndex Score
65 records- 0195US7278008B1Virtual address translation system with caching of variable-range translation clustersNVIDIA CORP·Filed 2004·Granted Oct 2, 2007·114 cites·33 claims
- 0294US7562205B1Virtual address translation system with caching of variable-range translation clustersNVIDIA CORP·Filed 2007·Granted Jul 14, 2009·34 cites·15 claims
- 0394US7334108B1Multi-client virtual address translation system with translation units of variable-range sizeNVIDIA CORP·Filed 2004·Granted Feb 19, 2008·108 cites·26 claims
- 0493US6779069B1Computer system with source-synchronous digital linkNVIDIA CORP·Filed 2002·Granted Aug 17, 2004·84 cites·22 claims
- 0592US7958483B1Clock throttling based on activity-level signalsNVIDIA CORP·Filed 2006·Granted Jun 7, 2011·32 cites·8 claims
- 0691US8760460B1Hardware-managed virtual buffers using a shared memory for load distributionKILGARIFF EMMETT M·Filed 2010·Granted Jun 24, 2014·41 cites·23 claims
- 0790US8327071B1Interprocessor direct cache writesDANSKIN JOHN M·Filed 2007·Granted Dec 4, 2012·25 cites·20 claims
- 0889US8060765B1Power estimation based on block activityCHA HUNGSE·Filed 2006·Granted Nov 15, 2011·41 cites·20 claims
- 0987US8941653B2Order-preserving distributed rasterizerNVIDIA CORP·Filed 2013·Granted Jan 27, 2015·8 cites·20 claims
- 1086US6647456B1High bandwidth-low latency memory controllerNVIDIA CORP·Filed 2001·Granted Nov 11, 2003·42 cites·56 claims
- 1183US8249819B1Virtual binningTREICHLER SEAN JEFFREY·Filed 2006·Granted Aug 21, 2012·14 cites·15 claims
- 1280US8775112B2System and method for increasing die yieldVAN DYKE JAMES M·Filed 2003·Granted Jul 8, 2014·17 cites·16 claims
- 1380US7042263B1Memory clock slowdown synthesis circuitNVIDIA CORP·Filed 2003·Granted May 9, 2006·28 cites·9 claims
- 1479US7966439B1Apparatus, system, and method for a fast data return memory controllerNVIDIA CORP·Filed 2004·Granted Jun 21, 2011·30 cites·21 claims
- 1578US6724395B1System, method and article of manufacture for anisotropic texture samplingNVIDIA CORP·Filed 2000·Granted Apr 20, 2004·24 cites·26 claims
- 1676US7385607B2Scalable shader architectureNVIDIA CORP·Filed 2004·Granted Jun 10, 2008·19 cites·44 claims
- 1776US7117238B1Method and system for performing pipelined reciprocal and reciprocal square root operationsNVIDIA CORP·Filed 2002·Granted Oct 3, 2006·23 cites·35 claims
- 1875US8984183B2Signaling, ordering, and execution of dynamically generated tasks in a processing systemPURCELL TIMOTHY JOHN·Filed 2011·Granted Mar 17, 2015·4 cites·19 claims
- 1975US8768642B2System and method for remotely configuring semiconductor functional circuitsDIAMOND MICHAEL B·Filed 2003·Granted Jul 1, 2014·12 cites·17 claims
- 2074US7406546B1Long-distance synchronous busNVIDIA CORP·Filed 2005·Granted Jul 29, 2008·7 cites·20 claims
- 2172US7852340B2Scalable shader architectureNVIDIA CORP·Filed 2007·Granted Dec 14, 2010·5 cites·16 claims
- 2272US7187220B1Memory clock slowdownNVIDIA CORP·Filed 2003·Granted Mar 6, 2007·13 cites·16 claims
- 2371US9164690B2System, method, and computer program product for copying data between memory locationsKHAILANY BRUCEK KURDO·Filed 2012·Granted Oct 20, 2015·3 cites·21 claims
- 2471US8307165B1Sorting requests to the DRAM for high page localityKEIL SHANE·Filed 2009·Granted Nov 6, 2012·5 cites·24 claims
- 2571US8077174B2Hierarchical processor arrayLINDHOLM JOHN ERIK·Filed 2007·Granted Dec 13, 2011·4 cites·25 claims
- 2670US8872833B2Integrated circuit configuration system and methodVAN DYKE JAMES M·Filed 2003·Granted Oct 28, 2014·9 cites·34 claims
- 2770US8587581B2Order-preserving distributed rasterizerMOLNAR STEVEN E·Filed 2009·Granted Nov 19, 2013·4 cites·20 claims
- 2869US7478289B1System and method for improving the yield of integrated circuits containing memoryNVIDIA CORP·Filed 2005·Granted Jan 13, 2009·7 cites·5 claims
- 2968US7809782B1Method and system for selecting a set of parametersNVIDIA CORP·Filed 2006·Granted Oct 5, 2010·4 cites·15 claims
- 3068US7523209B1Protocol and interface for source-synchronous digital linkNVIDIA CORP·Filed 2002·Granted Apr 21, 2009·10 cites·18 claims
- 3168US2025335196A1Application programming interface to wait on matrix multiply-accumulateNVIDIA CORP·Filed 2024·Application pending·0 cites
- 3267US7584321B1Memory address and datapath multiplexingNVIDIA CORP·Filed 2003·Granted Sep 1, 2009·9 cites·24 claims
- 3367US7287145B1System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devicesNVIDIA CORP·Filed 2004·Granted Oct 23, 2007·12 cites·21 claims
- 3466US7836318B1Memory clock slowdownNVIDIA CORP·Filed 2006·Granted Nov 16, 2010·4 cites·20 claims
- 3565US12204897B2Application programming interface to wait on matrix multiply-accumulateNVIDIA CORP·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
- 3663US7821520B1Fragment processor having dual mode register fileNVIDIA CORP·Filed 2004·Granted Oct 26, 2010·9 cites·26 claims
- 3763US6957298B1System and method for a high bandwidth-low latency memory controllerNVIDIA CORP·Filed 2003·Granted Oct 18, 2005·7 cites·26 claims
- 3862US8788996B2System and method for configuring semiconductor functional circuitsDIAMOND MICHAEL B·Filed 2003·Granted Jul 22, 2014·5 cites·31 claims
- 3961US12379959B2Compute task state encapsulationNVIDIA CORP·Filed 2020·Granted Aug 5, 2025·0 cites·22 claims
- 4058US8547993B1Asynchronous interface for communicating between clock domainsGARLICK LINCOLN G·Filed 2006·Granted Oct 1, 2013·2 cites·23 claims
- 4158US2025021622A1Efficient vector-matrix multiply operations across parallel processing unit threadsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 4257US9921873B2Controlling work distribution for processing tasksSHAH LACKY V·Filed 2012·Granted Mar 20, 2018·1 cites·18 claims
- 4357US7746349B1Method and apparatus for display of dataNVIDIA CORP·Filed 2005·Granted Jun 29, 2010·2 cites·18 claims
- 4456US7275143B1System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addressesNVIDIA CORP·Filed 2004·Granted Sep 25, 2007·4 cites·16 claims
- 4555US8041841B1Protocol and interface for source-synchronous digital linkNVIDIA CORP·Filed 2009·Granted Oct 18, 2011·0 cites·20 claims
- 4655US7240179B1System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devicesNVIDIA CORP·Filed 2004·Granted Jul 3, 2007·4 cites·6 claims
- 4751US8237705B2Hierarchical processor arrayLINDHOLM JOHN ERIK·Filed 2011·Granted Aug 7, 2012·0 cites·20 claims
- 4850US10795722B2Compute task state encapsulationDULUK JR JEROME F·Filed 2011·Granted Oct 6, 2020·0 cites·21 claims
- 4950US6980208B1System and method for enhancing depth value processing in a graphics pipelineNVIDIA CORP·Filed 2002·Granted Dec 27, 2005·3 cites·59 claims
- 5050US2025307149A1Scope tree consistency protocol for cache coherenceNVIDIA CORP·Filed 2024·Application pending·0 cites
Showing the top 50 of 65 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →