Inventor · disambiguated record
Shyam Agarwal
Also filed as: AGARWAL SHYAM KISHORE · AGARWAL Shyam
7 granted patents·1 pending application·24 citations·filing 1999–2020
80Inventor score
Top patents by PatentIndex Score
8 records- 0191US10103172B2Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE)SAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Oct 16, 2018·7 cites·15 claims
- 0281US10748932B2Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)SAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Aug 18, 2020·2 cites·20 claims
- 0377US10784864B1Low power integrated clock gating system and methodSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Sep 22, 2020·3 cites·9 claims
- 0466US11271011B2Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)SAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Mar 8, 2022·0 cites·16 claims
- 0562US10715118B2Flip-flop with single pre-charge nodeSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jul 14, 2020·1 cites·20 claims
- 0652US6281171B1MG-doped high-temperature superconductor having the superconducting anisotropy and method for producing the superconductorAGENCY IND SCIENCE TECHN·Filed 1999·Granted Aug 28, 2001·11 cites·4 claims
- 0733US2020044631A1D flip-flops with low clock dissipation powerSAMSUNG ELECTRONICS CO LTD·Filed 2018·Application pending·0 cites
- 0829US6605569B2Mg-doped high-temperature superconductor having low superconducting anisotropy and method for producing the superconductorAGENCY IND SCIENCE TECHN·Filed 2001·Granted Aug 12, 2003·0 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →