Inventor · disambiguated record
Sheldon Aronowitz
Also filed as: ARONOWITZ SHELDON
77 granted patents·3 pending applications·2,329 citations·filing 1985–2007
99Inventor score
Files withLSI LOGIC CORP54NAT SEMICONDUCTOR CORP19FAIRCHILD SEMICONDUCTOR2LSI CORP2NAT SEMICONDUCTOR INC1
Top patents by PatentIndex Score
80 records- 0195US6331468B1Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacersLSI LOGIC CORP·Filed 1998·Granted Dec 18, 2001·295 cites·18 claims
- 0294US6989565B1Memory device having an electron trapping layer in a high-K dielectric gate stackLSI LOGIC CORP·Filed 2003·Granted Jan 24, 2006·84 cites·5 claims
- 0394US6566262B1Method for creating self-aligned alloy capping layers for copper interconnect structuresLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·83 cites·23 claims
- 0494US6087229AComposite semiconductor gate dielectricsLSI LOGIC CORP·Filed 1998·Granted Jul 11, 2000·180 cites·26 claims
- 0592US6303047B1Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making sameLSI LOGIC CORP·Filed 1999·Granted Oct 16, 2001·81 cites·32 claims
- 0690US6413881B1Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting productLSI LOGIC CORP·Filed 2000·Granted Jul 2, 2002·60 cites·10 claims
- 0790US6033998AMethod of forming variable thickness gate dielectricsLSI LOGIC CORP·Filed 1998·Granted Mar 7, 2000·96 cites·22 claims
- 0889US5837598ADiffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making sameLSI LOGIC CORP·Filed 1997·Granted Nov 17, 1998·91 cites·15 claims
- 0986US5723896AIntegrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrateLSI LOGIC CORP·Filed 1996·Granted Mar 3, 1998·72 cites·12 claims
- 1085US6511925B1Process for forming high dielectric constant gate dielectric for integrated circuit structureLSI LOGIC CORP·Filed 2001·Granted Jan 28, 2003·32 cites·27 claims
- 1185US6156620AIsolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming sameLSI LOGIC CORP·Filed 1998·Granted Dec 5, 2000·82 cites·17 claims
- 1285US5376560AMethod for forming isolated semiconductor structuresNAT SEMICONDUCTOR CORP·Filed 1994·Granted Dec 27, 1994·70 cites·31 claims
- 1383US5441900ACMOS latchup suppression by localized minority carrier lifetime reductionNAT SEMICONDUCTOR CORP·Filed 1994·Granted Aug 15, 1995·51 cites·6 claims
- 1480US6572925B2Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric materialLSI LOGIC CORP·Filed 2001·Granted Jun 3, 2003·20 cites·21 claims
- 1578US5963801AMethod of forming retrograde well structures and punch-through barriers using low energy implantsLSI LOGIC CORP·Filed 1996·Granted Oct 5, 1999·60 cites·14 claims
- 1677US6858195B2Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric materialLSI LOGIC CORP·Filed 2001·Granted Feb 22, 2005·19 cites·34 claims
- 1777US5877530AFormation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantationLSI LOGIC CORP·Filed 1996·Granted Mar 2, 1999·44 cites·10 claims
- 1877US5312766AMethod of providing lower contact resistance in MOS transistorsNAT SEMICONDUCTOR CORP·Filed 1992·Granted May 17, 1994·68 cites·3 claims
- 1976US5893952AApparatus for rapid thermal processing of a waferLSI LOGIC CORP·Filed 1997·Granted Apr 13, 1999·38 cites·20 claims
- 2072US5585286AImplantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS deviceLSI LOGIC CORP·Filed 1995·Granted Dec 17, 1996·39 cites·16 claims
- 2172US5384477ACMOS latchup suppression by localized minority carrier lifetime reductionNAT SEMICONDUCTOR CORP·Filed 1993·Granted Jan 24, 1995·29 cites·6 claims
- 2271US6060375AProcess for forming re-entrant geometry for gate electrode of integrated circuit structureLSI LOGIC CORP·Filed 1996·Granted May 9, 2000·39 cites·13 claims
- 2371US5897381AMethod of forming a layer and semiconductor substrateLSI LOGIC CORP·Filed 1997·Granted Apr 27, 1999·30 cites·25 claims
- 2467US4746964AModification of properties of p-type dopants with other p-type dopantsFAIRCHILD SEMICONDUCTOR·Filed 1986·Granted May 24, 1988·31 cites·6 claims
- 2565US6930362B1Calcium doped polysilicon gate electrodesLSI LOGIC CORP·Filed 2003·Granted Aug 16, 2005·9 cites·25 claims
- 2665US4689667AMethod of controlling dopant diffusion and dopant electrical activation by implanted inert gas atomsFAIRCHILD SEMICONDUCTOR·Filed 1985·Granted Aug 25, 1987·30 cites·12 claims
- 2764US6673498B1Method for reticle formation utilizing metal vaporizationLSI LOGIC CORP·Filed 2001·Granted Jan 6, 2004·7 cites·19 claims
- 2864US5296387AMethod of providing lower contact resistance in MOS transistor structuresNAT SEMICONDUCTOR CORP·Filed 1992·Granted Mar 22, 1994·37 cites·2 claims
- 2963US7084408B1Vaporization and ionization of metals for use in semiconductor processingLSI LOGIC CORP·Filed 2003·Granted Aug 1, 2006·5 cites·23 claims
- 3063US6627556B1Method of chemically altering a silicon surface and associated electrical devicesLSI LOGIC CORP·Filed 2002·Granted Sep 30, 2003·7 cites·14 claims
- 3163US5468974AControl and modification of dopant distribution and activation in polysiliconLSI LOGIC CORP·Filed 1994·Granted Nov 21, 1995·36 cites·29 claims
- 3262US5904551AProcess for low energy implantation of semiconductor substrate using channeling to form retrograde wellsLSI LOGIC CORP·Filed 1996·Granted May 18, 1999·28 cites·12 claims
- 3362US5654210AProcess for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrateLSI LOGIC CORP·Filed 1995·Granted Aug 5, 1997·28 cites·14 claims
- 3462US5459085AGate array layout to accommodate multi angle ion implantationLSI LOGIC CORP·Filed 1994·Granted Oct 17, 1995·35 cites·1 claims
- 3562US5137838AMethod of fabricating P-buried layers for PNP devicesNAT SEMICONDUCTOR CORP·Filed 1991·Granted Aug 11, 1992·33 cites·7 claims
- 3661US5571744ADefect free CMOS processNAT SEMICONDUCTOR CORP·Filed 1993·Granted Nov 5, 1996·33 cites·14 claims
- 3760US7323228B1Method of vaporizing and ionizing metals for use in semiconductor processingLSI LOGIC CORP·Filed 2003·Granted Jan 29, 2008·3 cites·23 claims
- 3860US5296386AMethod of providing lower contact resistance in MOS transistor structuresNAT SEMICONDUCTOR CORP·Filed 1991·Granted Mar 22, 1994·34 cites·2 claims
- 3959US5707888AOxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidationLSI LOGIC CORP·Filed 1995·Granted Jan 13, 1998·21 cites·24 claims
- 4057US7670645B1Method of treating metal and metal salts to enable thin layer deposition in semiconductor processingLSI CORP·Filed 2007·Granted Mar 2, 2010·0 cites·21 claims
- 4156US7132336B1Method and apparatus for forming a memory structure having an electron affinity regionLSI LOGIC CORP·Filed 2002·Granted Nov 7, 2006·7 cites·15 claims
- 4256US6649219B2Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidationLSI LOGIC CORP·Filed 2001·Granted Nov 18, 2003·4 cites·35 claims
- 4356US5756369ARapid thermal processing using a narrowband infrared source and feedbackLSI LOGIC CORP·Filed 1996·Granted May 26, 1998·15 cites·13 claims
- 4456US5739580AOxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidationLSI LOGIC CORP·Filed 1997·Granted Apr 14, 1998·17 cites·8 claims
- 4555US5372952AMethod for forming isolated semiconductor structuresNAT SEMICONDUCTOR CORP·Filed 1992·Granted Dec 13, 1994·20 cites·23 claims
- 4653US7015168B2Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidationLSI LOGIC CORP·Filed 2003·Granted Mar 21, 2006·3 cites·12 claims
- 4753US5508211AMethod of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrateLSI LOGIC CORP·Filed 1994·Granted Apr 16, 1996·19 cites·12 claims
- 4852US6613651B1Integrated circuit isolation systemLSI LOGIC CORP·Filed 2000·Granted Sep 2, 2003·4 cites·12 claims
- 4952US5298435AApplication of electronic properties of germanium to inhibit n-type or p-type diffusion in siliconNAT SEMICONDUCTOR CORP·Filed 1992·Granted Mar 29, 1994·22 cites·15 claims
- 5052US5280185AApplication of electronic properties of germanium to inhibit n-type or p-type diffusion in siliconNAT SEMICONDUCTOR CORP·Filed 1991·Granted Jan 18, 1994·19 cites·6 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →