Inventor · disambiguated record
Sho Long Chen
Also filed as: CHEN SHO L · CHEN SHO LONG · CHEN SHO LONG S
16 granted patents·2 pending applications·652 citations·filing 1987–2009
95Inventor score
Top patents by PatentIndex Score
18 records- 0191US5493687ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1991·Granted Feb 20, 1996·103 cites·5 claims
- 0290US5560035ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·105 cites·8 claims
- 0389US5731850AHybrid hierarchial/full-search MPEG encoder motion estimationFiled 1995·Granted Mar 24, 1998·188 cites·17 claims
- 0487US7685402B2RISC microprocessor architecture implementing multiple typed register setsGARG SANJIV·Filed 2007·Granted Mar 23, 2010·10 cites·12 claims
- 0584US6249856B1RISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 2000·Granted Jun 19, 2001·26 cites·17 claims
- 0676US7409097B2Video encoding using variable bit ratesVWEB CORP·Filed 2003·Granted Aug 5, 2008·19 cites·21 claims
- 0776US6934332B1Motion estimation using predetermined pixel patterns and subpatternsVWEB CORP·Filed 2001·Granted Aug 23, 2005·17 cites·19 claims
- 0876US5838986ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1997·Granted Nov 17, 1998·42 cites·30 claims
- 0972US5682546ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1996·Granted Oct 28, 1997·35 cites·15 claims
- 1069US6044449ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1998·Granted Mar 28, 2000·31 cites·12 claims
- 1168US6813315B1Motion estimation using multiple search windowsVWEB CORP·Filed 2001·Granted Nov 2, 2004·15 cites·10 claims
- 1268US5610659AMPEG encoder that concurrently determines video data encoding format and rate controlFUTURETEL INC·Filed 1995·Granted Mar 11, 1997·48 cites·21 claims
- 1361US7555631B2RISC microprocessor architecture implementing multiple typed register setsGARG SANJIV·Filed 2002·Granted Jun 30, 2009·4 cites·15 claims
- 1458US7941636B2RISC microprocessor architecture implementing multiple typed register setsINTELLECTUAL VENTURE FUNDING LLC·Filed 2009·Granted May 10, 2011·0 cites·12 claims
- 1556US6891890B1Multi-phase motion estimation system and methodVWEB CORP·Filed 2001·Granted May 10, 2005·3 cites·9 claims
- 1645US2001034823A1RISC microprocessor architecture implementing multiple register setsFiled 2001·Application pending·0 cites
- 1743US2003202590A1Video encoding using direct mode predicted framesFiled 2002·Application pending·0 cites
- 1839US4837748ACounting RAMVITELIC CORP·Filed 1987·Granted Jun 6, 1989·6 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →