Inventor · disambiguated record
Shang-Tse Chuang
Also filed as: CHUANG SHANG-TSE
29 granted patents·15 pending applications·167 citations·filing 1999–2025
95Inventor score
Top patents by PatentIndex Score
44 records- 0193US8760958B2Methods and apparatus for designing and constructing multi-port memory circuits with voltage assistIYER SUNDAR·Filed 2012·Granted Jun 24, 2014·18 cites·18 claims
- 0288US8902672B2Methods and apparatus for designing and constructing multi-port memory circuitsIYER SUNDAR·Filed 2013·Granted Dec 2, 2014·13 cites·7 claims
- 0385US11151416B2Method and apparatus for efficiently processing convolution neural network operationsEXPEDERA INC·Filed 2019·Granted Oct 19, 2021·6 cites·20 claims
- 0483US12229589B2Method and apparatus for scheduling matrix operations in digital processing systemsEXPEDERA INC·Filed 2020·Granted Feb 18, 2025·2 cites·20 claims
- 0582US12008463B2Methods and apparatus for accessing external memory in a neural network processing systemEXPEDERA INC·Filed 2022·Granted Jun 11, 2024·1 cites·20 claims
- 0682US9520178B2Methods and apparatus for designing and constructing dual write memory circuits with voltage assistCISCO TECH INC·Filed 2015·Granted Dec 13, 2016·5 cites·20 claims
- 0780US8433880B2System and method for storing data in a virtualized high speed memory systemIYER SUNDAR·Filed 2009·Granted Apr 30, 2013·7 cites·14 claims
- 0876US8504796B2System and method for storing data in a virtualized high speed memory system with an integrated memory mapping tableIYER SUNDAR·Filed 2012·Granted Aug 6, 2013·3 cites·18 claims
- 0973US9293187B2Methods and apparatus for refreshing digital memory circuitsIYER SUNDAR·Filed 2011·Granted Mar 22, 2016·5 cites·21 claims
- 1073US9058860B2Methods and apparatus for synthesizing multi-port memory circuitsIYER SUNDAR·Filed 2012·Granted Jun 16, 2015·4 cites·12 claims
- 1173US2024265234A1Digital Processing Circuits and Methods of Matrix Operations in an Artificially Intelligent EnvironmentEXPEDERA INC·Filed 2024·Application pending·0 cites
- 1271US8838934B2System and method for storing data in a virtualized memory system with destructive readsMEMOIR SYSTEMS INC·Filed 2013·Granted Sep 16, 2014·4 cites·12 claims
- 1371US8677072B2System and method for reduced latency cachingIYER SUNDAR·Filed 2010·Granted Mar 18, 2014·3 cites·18 claims
- 1470US10042573B2High speed memory systems and methods for designing hierarchical memory systemsCISCO TECH INC·Filed 2016·Granted Aug 7, 2018·1 cites·20 claims
- 1570US6647019B1Packet-switch systemPMC SIERRA INC·Filed 1999·Granted Nov 11, 2003·74 cites·20 claims
- 1668US9442846B2High speed memory systems and methods for designing hierarchical memory systemsIYER SUNDAR·Filed 2010·Granted Sep 13, 2016·2 cites·22 claims
- 1766US9147466B2Methods and apparatus for designing and constructing dual write memory circuits with voltage assistCISCO TECH INC·Filed 2014·Granted Sep 29, 2015·2 cites·10 claims
- 1866US8266408B2System and method for storing data in a virtualized high speed memory systemIYER SUNDAR·Filed 2009·Granted Sep 11, 2012·2 cites·18 claims
- 1965US12182717B2Feature extraction with a convolutional neural networkEXPEDERA INC·Filed 2021·Granted Dec 31, 2024·0 cites·12 claims
- 2063US8935507B2System and method for storing multiple copies of data in a high speed memory systemMEMOIR SYSTEMS INC·Filed 2013·Granted Jan 13, 2015·1 cites·16 claims
- 2163US2025045122A1Machine learning model scalability with distributed multi-layer processingEXPEDERA INC·Filed 2024·Application pending·0 cites
- 2262US2025045569A1Methods and Apparatus For Recomputing Neural NetworksEXPEDERA INC·Filed 2024·Application pending·0 cites
- 2359US2025068914A1Efficient tensor operations using slicingEXPEDERA INC·Filed 2024·Application pending·0 cites
- 2458US7539199B2Switch fabric scheduling with fairness and priority considerationSHRIMALI GIREESH·Filed 2003·Granted May 26, 2009·13 cites·27 claims
- 2558US2025328562A1Systems and methods for heterogeneous large language model prompt attention-processingEXPEDERA INC·Filed 2025·Application pending·0 cites
- 2658US2024428046A1Methods And Apparatus For Managing Weight Data Accesses For Neural Network ProcessorsEXPEDERA INC·Filed 2023·Application pending·0 cites
- 2757US9063876B2System and method for simultaneously storing and read data from a memory systemMEMOIR SYSTEMS INC·Filed 2014·Granted Jun 23, 2015·0 cites·6 claims
- 2857US2025053614A1Systems and Processes for Data Reshape and Transport Using Matrix Processor CircuitsEXPEDERA INC·Filed 2024·Application pending·0 cites
- 2956US9390212B2Methods and apparatus for synthesizing multi-port memory circuitsCISCO TECH INC·Filed 2015·Granted Jul 12, 2016·1 cites·15 claims
- 3055US9280464B2System and method for simultaneously storing and reading data from a memory systemCISCO TECH INC·Filed 2015·Granted Mar 8, 2016·0 cites·16 claims
- 3155US2025061169A1Grid Sampling Methodologies in Neural Network Processor SystemsEXPEDERA INC·Filed 2023·Application pending·0 cites
- 3255US2025013259A1Methods and Devices for Clock Forwarding and RealignmentEXPEDERA INC·Filed 2024·Application pending·0 cites
- 3355US2025272145A1Systems and methods for heterogeneous large language model encoder and decoder processingEXPEDERA INC·Filed 2025·Application pending·0 cites
- 3454US9678669B2Hierarchical memory system compilerCISCO TECH INC·Filed 2013·Granted Jun 13, 2017·0 cites·19 claims
- 3553US11983616B2Methods and apparatus for constructing digital circuits for performing matrix operationsEXPEDERA INC·Filed 2018·Granted May 14, 2024·0 cites·10 claims
- 3651US2024427839A1Methods And Apparatus For Matrix Processing In A Neural Network Processing SystemEXPEDERA INC·Filed 2023·Application pending·0 cites
- 3749US2024377853A1Power-Efficient Clocking and Clock ShapingEXPEDERA INC·Filed 2023·Application pending·0 cites
- 3848US8589851B2Intelligent memory system compilerIYER SUNDAR·Filed 2010·Granted Nov 19, 2013·0 cites·10 claims
- 3948US2024152761A1Method and apparatus for using a packet architecture to process neural networks in a neural processing unitEXPEDERA INC·Filed 2022·Application pending·0 cites
- 4047US12141226B2Systems and processes for organizing and controlling multiple matrix processor circuitsEXPEDERA INC·Filed 2019·Granted Nov 12, 2024·0 cites·16 claims
- 4147US7624224B1System and method for directly executing code from block-based memoryNVIDIA CORP·Filed 2005·Granted Nov 24, 2009·0 cites·25 claims
- 4244US2007066415A1Training deviceHOU WEN-SUN·Filed 2005·Application pending·0 cites
- 4342US9965211B2Dynamic packet buffers with consolidation of low utilized memory banksCISCO TECH INC·Filed 2016·Granted May 8, 2018·0 cites·20 claims
- 4434US2014104960A1Methods and Apparatus for Designing and Constructing High-Speed Memory CircuitsIYER SUNDAR·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →