Inventor · disambiguated record
Shu-Rong Chun
Also filed as: CHUN SHU-RONG
21 granted patents·9 pending applications·36 citations·filing 2018–2025
92Inventor score
Technology areasH10W
Top patents by PatentIndex Score
30 records- 0198US11508656B2Semiconductor package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 22, 2022·8 cites·20 claims
- 0298US11502013B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 15, 2022·4 cites·20 claims
- 0394US10978382B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Apr 13, 2021·8 cites·20 claims
- 0492US11183487B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Nov 23, 2021·9 cites·20 claims
- 0586US2025336784A1Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0683US2025096203A1Manufacturing method of semiconductor packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0782US11049805B2Semiconductor package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 29, 2021·2 cites·19 claims
- 0882US11004758B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 11, 2021·2 cites·20 claims
- 0982US2024297114A1Methods of forming semiconductor packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1081US11004827B2Semiconductor package and manufacturing method of semiconductor packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 11, 2021·2 cites·20 claims
- 1179US12412817B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 9, 2025·0 cites·20 claims
- 1279US12014979B2Methods of forming semiconductor packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 18, 2024·0 cites·20 claims
- 1379US2024395769A1Bonding passive devices on active dies to form 3d packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1478US12166015B2Semiconductor package and manufacturing method of semiconductor packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 10, 2024·0 cites·20 claims
- 1578US11990381B2Integrated circuit packages having support ringsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 21, 2024·0 cites·20 claims
- 1677US2025349732A1Semiconductor package and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1776US12255174B2Bonding passive devices on active dies to form 3D packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Mar 18, 2025·0 cites·20 claims
- 1875US2024371726A1Integrated Circuit Package and MethodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1974US11488897B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 1, 2022·0 cites·20 claims
- 2074US2025323107A1Method of forming semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2173US12300571B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 13, 2025·0 cites·20 claims
- 2273US11107771B2Segregated power and ground design for yield improvementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 31, 2021·1 cites·19 claims
- 2371US11646296B2Semiconductor package and manufacturing method of semiconductor packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted May 9, 2023·0 cites·20 claims
- 2469US11837575B2Bonding passive devices on active device dies to form 3D packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 5, 2023·0 cites·20 claims
- 2566US11804443B2Segregated power and ground design for yield improvementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Oct 31, 2023·0 cites·20 claims
- 2666US2023307375A1Semiconductor Package and Method of Forming the SameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2761US12374592B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jul 29, 2025·0 cites·14 claims
- 2853US2024019486A1Alignment Mark Design for Wafer-Level Testing and Method Forming the SameTAIWAN SEMICONDUCTOR MAMUFACTURING CO LTD·Filed 2023·Application pending·0 cites
- 2952US11121070B2Integrated fan-out packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 3051US11538735B2Method of forming integrated circuit packages with mechanical bracesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 27, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →