Inventor · disambiguated record
Sherif Eid
Also filed as: EID SHERIF
11 granted patents·1 pending application·91 citations·filing 2007–2022
91Inventor score
Top patents by PatentIndex Score
12 records- 0196US10671700B2Systems and methods for obfuscating a circuit designEFABLESS CORP·Filed 2019·Granted Jun 2, 2020·16 cites·22 claims
- 0295US10452802B2Methods for engineering integrated circuit design and developmentEFABLESS CORP·Filed 2017·Granted Oct 22, 2019·12 cites·21 claims
- 0394US11301609B2Systems and methods for obfuscating a circuit designEFABLESS CORP·Filed 2020·Granted Apr 12, 2022·3 cites·21 claims
- 0492US10437953B2Systems for engineering integrated circuit design and developmentEFABLESS CORP·Filed 2017·Granted Oct 8, 2019·7 cites·12 claims
- 0592US10423748B2Systems and methods for obfuscating a circuit designEFABLESS CORP·Filed 2017·Granted Sep 24, 2019·6 cites·19 claims
- 0689US11748541B2Methods for engineering integrated circuit design and developmentEFABLESS CORP·Filed 2021·Granted Sep 5, 2023·1 cites·20 claims
- 0788US11182526B2Methods for engineering integrated circuit design and developmentEFABLESS CORP·Filed 2019·Granted Nov 23, 2021·3 cites·26 claims
- 0882US8063805B1Digital feedback technique for regulatorsEID SHERIF·Filed 2009·Granted Nov 22, 2011·14 cites·21 claims
- 0982US7906982B1Interface apparatus and methods of testing integrated circuits using the sameCYPRESS SEMICONDUCTOR CORP·Filed 2007·Granted Mar 15, 2011·21 cites·19 claims
- 1078US8254200B2System and method to compensate for process and environmental variations in semiconductor devicesEID SHERIF·Filed 2010·Granted Aug 28, 2012·8 cites·18 claims
- 1178US2022277126A1Systems and methods for obfuscating a circuit designEFABLESS CORP·Filed 2022·Application pending·0 cites
- 1276US11775722B2Systems and methods for obfuscating a circuit designEFABLESS CORP·Filed 2021·Granted Oct 3, 2023·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →