Inventor · disambiguated record
Shail Aditya Gupta
Also filed as: GUPTA SHAIL ADITYA · SCHLANSKER MICHAEL S
30 granted patents·2 pending applications·1,193 citations·filing 1999–2022
97Inventor score
Top patents by PatentIndex Score
32 records- 0197US10802807B1Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2019·Granted Oct 13, 2020·25 cites·20 claims
- 0296US11281440B1Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2020·Granted Mar 22, 2022·5 cites·20 claims
- 0396US6507947B1Programmatic synthesis of processor element arraysHEWLETT PACKARD CO·Filed 1999·Granted Jan 14, 2003·402 cites·27 claims
- 0494US11113030B1Constraints for applications in a heterogeneous programming environmentXILINX INC·Filed 2019·Granted Sep 7, 2021·18 cites·20 claims
- 0594US10628622B1Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architectureXILINX INC·Filed 2019·Granted Apr 21, 2020·27 cites·20 claims
- 0690US6408428B1Automated design of processor systems using feedback from internal measurements of candidate systemsHEWLETT PACKARD CO·Filed 1999·Granted Jun 18, 2002·161 cites·17 claims
- 0789US9680893B2Method and system for event state management in stream processingYAHOO INC·Filed 2013·Granted Jun 13, 2017·13 cites·17 claims
- 0889US6651222B2Automatic design of VLIW processorsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Nov 18, 2003·45 cites·20 claims
- 0989US6385757B1Auto design of VLIW processorsHEWLETT PACKARD CO·Filed 1999·Granted May 7, 2002·120 cites·24 claims
- 1088US11301295B1Implementing an application specified as a data flow graph in an array of data processing enginesXILINX INC·Filed 2019·Granted Apr 12, 2022·8 cites·20 claims
- 1188US6952816B2Methods and apparatus for digital circuit design generationHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 4, 2005·57 cites·56 claims
- 1287US11204745B2Dataflow graph programming environment for a heterogenous processing systemXILINX INC·Filed 2019·Granted Dec 21, 2021·4 cites·18 claims
- 1386US10872057B1Partitioning in a compiler flow for a heterogeneous multi-core architectureXILINX INC·Filed 2019·Granted Dec 22, 2020·6 cites·20 claims
- 1486US6457173B1Automatic design of VLIW instruction formatsHEWLETT PACKARD CO·Filed 1999·Granted Sep 24, 2002·125 cites·20 claims
- 1584US10860766B1Compilation flow for a heterogeneous multi-core architectureXILINX INC·Filed 2019·Granted Dec 8, 2020·4 cites·20 claims
- 1683US10891132B2Flow convergence during hardware-software design for heterogeneous and programmable devicesXILINX INC·Filed 2019·Granted Jan 12, 2021·4 cites·20 claims
- 1783US6581187B2Automatic design of VLIW processorsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 17, 2003·27 cites·22 claims
- 1876US11188312B2Hardware-software design flow with high-level synthesis for heterogeneous and programmable devicesXILINX INC·Filed 2019·Granted Nov 30, 2021·2 cites·18 claims
- 1974US10891414B2Hardware-software design flow for heterogeneous and programmable devicesXILINX INC·Filed 2019·Granted Jan 12, 2021·2 cites·20 claims
- 2072US11687327B2Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2022·Granted Jun 27, 2023·0 cites·20 claims
- 2172US7107199B2Method and system for the design of pipelines of processorsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 12, 2006·17 cites·17 claims
- 2268US6629312B1Programmatic synthesis of a machine description for retargeting a compilerHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Sep 30, 2003·50 cites·18 claims
- 2367US7096438B2Method of using clock cycle-time in determining loop schedules during circuit designHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Aug 22, 2006·13 cites·39 claims
- 2466US11645053B2Hardware-software design flow with high-level synthesis for heterogeneous and programmable devicesXILINX INC·Filed 2021·Granted May 9, 2023·0 cites·20 claims
- 2564US7484079B2Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stagesHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 27, 2009·11 cites·30 claims
- 2663US2022058005A1Dataflow graph programming environment for a heterogenous processing systemXILINX INC·Filed 2021·Application pending·0 cites
- 2762US7000137B2System for and method of clock cycle-time analysis using mode-slicing mechanismHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Feb 14, 2006·9 cites·62 claims
- 2858US6766445B2Storage system for use in custom loop accelerators and the likeHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 20, 2004·6 cites·15 claims
- 2949US6966043B2Method for designing minimal cost, timing correct hardware during circuit synthesisHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Nov 15, 2005·1 cites·26 claims
- 3046US2008082707A1Non-blocking bus controller for a pipelined, variable latency, hierarchical bus with point-to-point first-in first-out orderingSYNFORA INC·Filed 2007·Application pending·0 cites
- 3144US6490716B1Automated design of processor instruction unitsHEWLETT PACKARD CO·Filed 1999·Granted Dec 3, 2002·17 cites·9 claims
- 3242US6853970B1Automatic design of processor datapathsHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Feb 8, 2005·14 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →