Inventor · disambiguated record
Shu-Yi Kao
Also filed as: KAO SHU-YI
20 granted patents·4 pending applications·6 citations·filing 2011–2022
88Inventor score
Top patents by PatentIndex Score
24 records- 0166US10936784B2Planning method for power metal linesREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Mar 2, 2021·1 cites·10 claims
- 0265US9003341B2Method for determining interface timing of integrated circuit automatically and related machine readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted Apr 7, 2015·2 cites·19 claims
- 0363US9858382B2Computer program product for timing analysis of integrated circuitREALTEK SEMICONDUCTOR CORP·Filed 2015·Granted Jan 2, 2018·1 cites·6 claims
- 0460US10657303B2Circuit encoding method and circuit structure recognition methodREALTEK SEMICONDUCTOR CORP·Filed 2018·Granted May 19, 2020·1 cites·11 claims
- 0560US8726206B1Deadlock detection method and related machine readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted May 13, 2014·1 cites·14 claims
- 0655US12488168B2Circuit verification methodREALTEK SEMICONDUCTOR CORP·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 0753US11194945B1Clock deadlock detecting system, method, and non-transitory computer readable storage mediumREALTEK SEMICONDUCTOR CORP·Filed 2021·Granted Dec 7, 2021·0 cites·20 claims
- 0852US11455449B2Method for determining IC voltage and method for finding relation between voltages and circuit parametersREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Sep 27, 2022·0 cites·12 claims
- 0952US10909290B2Method of detecting a circuit malfunction and related deviceREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Feb 2, 2021·0 cites·8 claims
- 1051US11010521B2Method of detecting relations between pins of circuit and computer program product thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted May 18, 2021·0 cites·18 claims
- 1151US10860758B2Method of using simulation software to generate circuit layoutREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Dec 8, 2020·0 cites·18 claims
- 1251US10778214B1Circuit structure and power-on method thereofREALTEK SEMICONDUCTOR CORP·Filed 2019·Granted Sep 15, 2020·0 cites·14 claims
- 1350US11314912B2IC design data base generating method, IC design method, and electronic device using the methodsREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Apr 26, 2022·0 cites·16 claims
- 1448US10783293B2Circuit design system, checking method, and non-transitory computer readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2018·Granted Sep 22, 2020·0 cites·20 claims
- 1547US10521529B2Simulation method for mixed-signal circuit system and related electronic deviceREALTEK SEMICONDUCTOR CORP·Filed 2017·Granted Dec 31, 2019·0 cites·8 claims
- 1646US11959956B2Circuit check method and electronic apparatusREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Apr 16, 2024·0 cites·8 claims
- 1745US10997353B2Integrated circuit design method and non-transitory computer readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted May 4, 2021·0 cites·10 claims
- 1845US2015067623A1Timing analysis method for non-standard cell circuit and associated machine readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2014·Application pending·0 cites
- 1944US2019384868A1Method and apparatus for adaptive voltage scaling to eliminate delay variation of whole designREALTEK SEMICONDUCTOR CORP·Filed 2019·Application pending·0 cites
- 2043US8713497B2Method of generating integrated circuit modelREALTEK SEMICONDUCTOR CORP·Filed 2013·Granted Apr 29, 2014·0 cites·9 claims
- 2142US2013298095A1Method for checking i/o cell connections and associated computer readable mediumREALTEK SEMICONDUCTOR CORP·Filed 2013·Application pending·0 cites
- 2241US11416665B2Power rail design method, apparatus and non-transitory computer readable medium thereofREALTEK SEMICONDUCTOR CORP·Filed 2020·Granted Aug 16, 2022·0 cites·11 claims
- 2339US2020285791A1Circuit design method and associated computer program productREALTEK SEMICONDUCTOR CORP·Filed 2020·Application pending·0 cites
- 2435US8443320B2Extracting methods for circuit modelsLEE MENG-JUNG·Filed 2011·Granted May 14, 2013·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →