Inventor · disambiguated record
Shakti Kapoor
Also filed as: KAPOOR SHAKTI
84 granted patents·6 pending applications·301 citations·filing 1999–2023
99Inventor score
Top patents by PatentIndex Score
90 records- 0196US9612929B1Efficient validation/verification of coherency and snoop filtering mechanisms in computing systemsIBM·Filed 2016·Granted Apr 4, 2017·16 cites·15 claims
- 0296US9594680B1Identifying stale entries in address translation cacheIBM·Filed 2016·Granted Mar 14, 2017·16 cites·1 claims
- 0392US9542290B1Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted Jan 10, 2017·7 cites·3 claims
- 0490US10169186B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·5 cites·15 claims
- 0590US7752499B2System and method for using resource pools and instruction pools for processor design verification and validationIBM·Filed 2007·Granted Jul 6, 2010·25 cites·20 claims
- 0690US7647539B2System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validationIBM·Filed 2007·Granted Jan 12, 2010·29 cites·18 claims
- 0788US10169185B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·4 cites·11 claims
- 0886US9747396B1Driving pervasive commands using breakpoints in a hardware-accelerated simulation environmentIBM·Filed 2016·Granted Aug 29, 2017·4 cites·18 claims
- 0986US7669083B2System and method for re-shuffling test case instruction orders for processor design verification and validationIBM·Filed 2007·Granted Feb 23, 2010·22 cites·20 claims
- 1084US7992059B2System and method for testing a large memory area during processor design verification and validationIBM·Filed 2007·Granted Aug 2, 2011·15 cites·20 claims
- 1183US8832502B2Hardware verification using acceleration platformDUSANAPUDI MANOJ·Filed 2012·Granted Sep 9, 2014·11 cites·16 claims
- 1283US7747908B2System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 29, 2010·14 cites·20 claims
- 1382US7797650B2System and method for testing SLB and TLB cells during processor design verification and validationIBM·Filed 2007·Granted Sep 14, 2010·14 cites·20 claims
- 1478US7661023B2System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validationIBM·Filed 2007·Granted Feb 9, 2010·9 cites·20 claims
- 1577US10169180B2Replicating test code and test data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted Jan 1, 2019·2 cites·19 claims
- 1677US9921897B2Testing a non-core MMUIBM·Filed 2016·Granted Mar 20, 2018·2 cites·10 claims
- 1776US9940226B2Synchronization of hardware agents in a computer systemIBM·Filed 2016·Granted Apr 10, 2018·2 cites·15 claims
- 1876US9501408B2Efficient validation of coherency between processor cores and accelerators in computer systemsGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 22, 2016·4 cites·13 claims
- 1975US6792514B2Method, system and computer program product to stress and test logical partition isolation featuresIBM·Filed 2001·Granted Sep 14, 2004·23 cites·26 claims
- 2074US12130749B2Validation of store coherence relative to page translation invalidationIBM·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 2174US9697138B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Jul 4, 2017·1 cites·1 claims
- 2274US7739570B2System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 15, 2010·7 cites·20 claims
- 2374US7584394B2System and method for pseudo-random test pattern memory allocation for processor design verification and validationIBM·Filed 2007·Granted Sep 1, 2009·7 cites·20 claims
- 2473US10521355B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2017·Granted Dec 31, 2019·1 cites·20 claims
- 2573US8099559B2System and method for generating fast instruction and data interrupts for processor design verification and validationCHOUDHURY SHUBHODEEP ROY·Filed 2007·Granted Jan 17, 2012·9 cites·20 claims
- 2672US7966521B2Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnosticsIBM·Filed 2008·Granted Jun 21, 2011·5 cites·20 claims
- 2771US8037215B2Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systemsIBM·Filed 2008·Granted Oct 11, 2011·4 cites·4 claims
- 2870US10223225B2Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundariesIBM·Filed 2016·Granted Mar 5, 2019·1 cites·20 claims
- 2968US7689886B2System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validationIBM·Filed 2007·Granted Mar 30, 2010·7 cites·20 claims
- 3067US11620235B1Validation of store coherence relative to page translation invalidationIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3164US11163704B2Method, system, and apparatus for reducing processor latencyIBM·Filed 2019·Granted Nov 2, 2021·0 cites·20 claims
- 3263US11347505B2Processor performance monitor that logs reasons for reservation lossIBM·Filed 2020·Granted May 31, 2022·0 cites·17 claims
- 3363US11061821B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2019·Granted Jul 13, 2021·0 cites·20 claims
- 3463US10489261B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 26, 2019·0 cites·16 claims
- 3563US10481991B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 19, 2019·0 cites·19 claims
- 3663US8145819B2Method and system for stealing interrupt vectorsALAPATI SANGRAM·Filed 2007·Granted Mar 27, 2012·4 cites·16 claims
- 3762US10713179B2Efficiently generating effective address translations for memory management test casesIBM·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 3862US10489259B2Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2018·Granted Nov 26, 2019·0 cites·10 claims
- 3962US10261917B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Apr 16, 2019·0 cites·14 claims
- 4061US12450411B2Hazard generating for speculative cores in a microprocessorIBM·Filed 2021·Granted Oct 21, 2025·0 cites·20 claims
- 4161US8127192B2Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt modeARORA SAMPAN·Filed 2008·Granted Feb 28, 2012·4 cites·20 claims
- 4259US10482040B2Method, system, and apparatus for reducing processor latencyIBM·Filed 2017·Granted Nov 19, 2019·0 cites·20 claims
- 4359US9720845B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Aug 1, 2017·0 cites·1 claims
- 4459US7793011B2Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systemsIBM·Filed 2008·Granted Sep 7, 2010·1 cites·12 claims
- 4558US10540249B2Stress testing a processor memory with a link stackIBM·Filed 2017·Granted Jan 21, 2020·0 cites·15 claims
- 4658US9959182B2Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted May 1, 2018·0 cites·6 claims
- 4758US8019566B2System and method for efficiently testing cache congruence classes during processor design verification and validationIBM·Filed 2007·Granted Sep 13, 2011·1 cites·20 claims
- 4858US8006221B2System and method for testing multiple processor modes for processor design verification and validationIBM·Filed 2007·Granted Aug 23, 2011·2 cites·20 claims
- 4957US10261878B2Stress testing a processor memory with a link stackIBM·Filed 2017·Granted Apr 16, 2019·0 cites·12 claims
- 5057US9892060B2Identifying stale entries in address translation cacheIBM·Filed 2015·Granted Feb 13, 2018·0 cites·20 claims
Showing the top 50 of 90 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Shakti Kapoor files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →