Inventor · disambiguated record
Shozo Kawabata
Also filed as: KAWABATA SHOZO
10 granted patents·58 citations·filing 2003–2015
88Inventor score
Top patents by PatentIndex Score
10 records- 0176US8023341B2Method and apparatus for address allotting and verification in a semiconductor deviceSPANSION LLC·Filed 2010·Granted Sep 20, 2011·4 cites·12 claims
- 0273US6862217B2Control method of non-volatile semiconductor memory cell and non-volatile semiconductor memory deviceFUJITSU LTD·Filed 2003·Granted Mar 1, 2005·23 cites·22 claims
- 0371US7415568B2Method and apparatus for initialization control in a non-volatile memory deviceSPANSION LLC·Filed 2005·Granted Aug 19, 2008·8 cites·12 claims
- 0469US7120050B2Method and apparatus for setting operational information of a non-volatile memorySPANSION LLC·Filed 2005·Granted Oct 10, 2006·7 cites·15 claims
- 0567US7452771B2Method for fabricating a semiconductor deviceFUJITSU LTD·Filed 2005·Granted Nov 18, 2008·3 cites·6 claims
- 0662US9484341B2Mom capacitor circuit and semiconductor device thereofPOWERCHIP TECH CORP·Filed 2015·Granted Nov 1, 2016·1 cites·17 claims
- 0762US7859914B2Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is variedSPANSION LLC·Filed 2008·Granted Dec 28, 2010·5 cites·13 claims
- 0854US6977411B2Semiconductor device comprising transistors having control gates and floating gate electrodesFUJITSU LTD·Filed 2003·Granted Dec 20, 2005·5 cites·19 claims
- 0949US7813154B2Method and apparatus for address allotting and verification in a semiconductor deviceSPANSION LLC·Filed 2008·Granted Oct 12, 2010·1 cites·9 claims
- 1048US7433219B2Method and apparatus for address allotting and verification in a semiconductor deviceSPANSION LLC·Filed 2006·Granted Oct 7, 2008·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →