Inventor · disambiguated record
Sheau Jiung Lee
Also filed as: LEE SHEAU JIUNG
18 granted patents·131 citations·filing 1989–2024
93Inventor score
Files withACER INC7UNIV CALIFORNIA5CHIPLEGO TECH SHANGHAI CO LTD1CHIPLITE TECH CO LTD1SARATOGA MILKYWAY INC1
Top patents by PatentIndex Score
18 records- 0192US11669474B1Bus pipeline structure for die-to-die interconnect and chipCHIPLEGO TECH SHANGHAI CO LTD·Filed 2022·Granted Jun 6, 2023·17 cites·18 claims
- 0279US9426016B2Self track scheme for multi frequency band serializer de-serializer I/O circuitsUNIV CALIFORNIA·Filed 2015·Granted Aug 23, 2016·3 cites·20 claims
- 0379US5206833APipelined dual port RAMACER INC·Filed 1991·Granted Apr 27, 1993·49 cites·2 claims
- 0468US12430270B1Multi-port SRAM system for a distributed memory poolTEXAS MILKYWAY INC·Filed 2024·Granted Sep 30, 2025·0 cites·16 claims
- 0567US10614027B2Serial bus with embedded side band communicationTSVLINK CORP·Filed 2016·Granted Apr 7, 2020·2 cites·5 claims
- 0667US5218246AMOS analog XOR amplifierACER INC·Filed 1990·Granted Jun 8, 1993·21 cites·10 claims
- 0764US9369318B2Scalable serial/de-serial I/O for chip-to-chip connection based on multi-frequency QAM schemeUNIV CALIFORNIA·Filed 2015·Granted Jun 14, 2016·2 cites·32 claims
- 0861US9712368B2Differential current mode low latency modulation and demodulation for chip-to-chip connectionUNIV CALIFORNIA·Filed 2015·Granted Jul 18, 2017·1 cites·24 claims
- 0958US9356582B2Low jitter tunable voltage control oscillator with self calibration circuits to reduce chip fabrication process variationUNIV CALIFORNIA·Filed 2015·Granted May 31, 2016·1 cites·20 claims
- 1049US12326812B2System cache architecture for supporting multiprocessor architecture, and chipCHIPLITE TECH CO LTD·Filed 2023·Granted Jun 10, 2025·0 cites·20 claims
- 1148US5329632ACache memory system, and comparator and MOS analog XOR amplifier for use in the systemACER INC·Filed 1993·Granted Jul 12, 1994·7 cites·17 claims
- 1247US12380048B2Hybrid system fabric for enabling host operating system and real-time operating system within chiplet system-on-chipSARATOGA MILKYWAY INC·Filed 2021·Granted Aug 5, 2025·0 cites·19 claims
- 1347US5254890AGround bouncing reducing circuit and methodACER INC·Filed 1992·Granted Oct 19, 1993·9 cites·13 claims
- 1443US5319348ACache memory system, and comparator and MOS analog XOR amplifier for use in the systemACER INC·Filed 1993·Granted Jun 7, 1994·11 cites·21 claims
- 1540US9491028B2Phase synchronization of modulation or demodulation for QAM-based multiband TSV-linkUNIV CALIFORNIA·Filed 2015·Granted Nov 8, 2016·0 cites·20 claims
- 1637US10713170B2Multiple channel cache memory and system memory device utilizing a pseudo-multiple port for commands and addresses and a multiple frequency band QAM serializer/deserializer for dataTSVLINK CORP A DELAWARE CORP·Filed 2017·Granted Jul 14, 2020·0 cites·16 claims
- 1734US5329633ACache memory system, and comparator and MOS analog XOR amplifier for use in the systemACER INC·Filed 1993·Granted Jul 12, 1994·5 cites·20 claims
- 1833US5004938AMOS analog NOR amplifier and current source thereforACER INC·Filed 1989·Granted Apr 2, 1991·3 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →