Inventor · disambiguated record
Shailesh Kumar Madisetti
Also filed as: MADISETTI SHAILESH KUMAR
1 granted patent·6 pending applications·0 citations·filing 2021–2023
10Inventor score
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7 records- 0154US2025098179A1Memory layers at opposing sides of a complementary metal-oxide semiconductor layerSHARMA ABHISHEK A·Filed 2023·Application pending·0 cites
- 0250US12432979B2Gate dielectric for thin film oxide transistorsINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·20 claims
- 0347US2023369508A1Multi-layered or graded semiconductor region in thin film transistor (tft) structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 0446US2023371233A1Multi-tier memory structure with graded characteristicsINTEL CORP·Filed 2022·Application pending·0 cites
- 0546US2023369509A1Doping contacts of thin film transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 0644US2023369444A1Multi-layered or graded gate dielectric in thin film transistor (tft) structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 0743US2022359758A1Metal oxide thin film transistors with multi-composition gate dielectricINTEL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →