Inventor · disambiguated record
Shigeru Nagasawa
Also filed as: NAGASAWA SHIGERU
17 granted patents·564 citations·filing 1975–1998
95Inventor score
Top patents by PatentIndex Score
17 records- 0183US5592628AData communication system which guarantees at a transmission station the arrival of transmitted data to a receiving station and method thereofFUJITSU LTD·Filed 1996·Granted Jan 7, 1997·124 cites·27 claims
- 0277US5557744AMultiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processorsFUJITSU LTD·Filed 1993·Granted Sep 17, 1996·76 cites·8 claims
- 0375US5625846ATransfer request queue control system using flags to indicate transfer request queue validity and whether to use round-robin system for dequeuing the corresponding queuesFUJITSU LTD·Filed 1993·Granted Apr 29, 1997·69 cites·16 claims
- 0473US4293941AMemory access control system in vector processing systemFUJITSU LTD·Filed 1979·Granted Oct 6, 1981·35 cites·2 claims
- 0570US6189414B1Counter plate and cutting die for die cutting machineYOSHIZAWA INDUSTRY INC·Filed 1998·Granted Feb 20, 2001·27 cites·7 claims
- 0666US5572680AMethod and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor numberFUJITSU LTD·Filed 1993·Granted Nov 5, 1996·47 cites·6 claims
- 0761US5896501AMultiprocessor system and parallel processing method for processing data transferred between processorsFUJITSU LTD·Filed 1997·Granted Apr 20, 1999·41 cites·8 claims
- 0856US5623688AParallel processing system including instruction processor to execute instructions and transfer processor to transfer data for each user programFUJITSU LTD·Filed 1995·Granted Apr 22, 1997·34 cites·11 claims
- 0955US5822785AData transfer using local and global address translation and authorizationFUJITSU LTD·Filed 1997·Granted Oct 13, 1998·30 cites·24 claims
- 1048US5652905AData processing unitFUJITSU LTD·Filed 1995·Granted Jul 29, 1997·19 cites·6 claims
- 1146US5832261ABarrier synchronizing mechanism for a parallel data processing control systemFUJITSU LTD·Filed 1992·Granted Nov 3, 1998·20 cites·5 claims
- 1245US4143330ADetector circuitTOKYO SHIBAURA ELECTRIC CO·Filed 1977·Granted Mar 6, 1979·6 cites·3 claims
- 1342US4467226ADarlington complementary circuit for preventing zero crossover distortionTOKYO SHIBAURA ELECTRIC CO·Filed 1981·Granted Aug 21, 1984·5 cites·3 claims
- 1438US5634071ASynchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallelFUJITSU LTD·Filed 1996·Granted May 27, 1997·11 cites·33 claims
- 1538US3976866AAddition control systemFUJITSU LTD·Filed 1975·Granted Aug 24, 1976·8 cites·12 claims
- 1637US5664104ATransfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unitFUJITSU LTD·Filed 1993·Granted Sep 2, 1997·8 cites·2 claims
- 1732US5592680AAbnormal packet processing systemFUJITSU LTD·Filed 1995·Granted Jan 7, 1997·4 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →