Inventor · disambiguated record
Shahzad Nazar
Also filed as: NAZAR SHAHZAD
10 granted patents·2 pending applications·29 citations·filing 2010–2025
85Inventor score
Top patents by PatentIndex Score
12 records- 0195US11152046B1Sram bit cell retentionAPPLE INC·Filed 2020·Granted Oct 19, 2021·6 cites·20 claims
- 0286US11914973B2Performing multiple bit computation and convolution in memoryAPPLE INC·Filed 2020·Granted Feb 27, 2024·2 cites·20 claims
- 0385US10523194B2Low leakage power switchAPPLE INC·Filed 2017·Granted Dec 31, 2019·5 cites·18 claims
- 0483US2025355626A1Performing Multiple Bit Computation and Convolution in MemoryAPPLE INC·Filed 2025·Application pending·0 cites
- 0582US8811109B2Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methodsTERZIOGLU ESIN·Filed 2012·Granted Aug 19, 2014·7 cites·26 claims
- 0681US12408317B2SRAM macro design architectureAPPLE INC·Filed 2023·Granted Sep 2, 2025·0 cites·20 claims
- 0778US12379899B2Performing multiple bit computation and convolution in memoryAPPLE INC·Filed 2024·Granted Aug 5, 2025·0 cites·20 claims
- 0878US11094395B2Retention voltage management for a volatile memoryAPPLE INC·Filed 2019·Granted Aug 17, 2021·4 cites·20 claims
- 0973US9036446B2Global reset with replica for pulse latch pre-decodersQUALCOMM INC·Filed 2012·Granted May 19, 2015·4 cites·9 claims
- 1072US11004482B1Retention voltage generator circuitAPPLE INC·Filed 2020·Granted May 11, 2021·1 cites·20 claims
- 1158US11688486B2Retention voltage management for a volatile memoryAPPLE INC·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 1231US2011219266A1System and Method of Testing an Error Correction ModuleQUALCOMM INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →