Inventor · disambiguated record
Shashank Nemawarkar
Also filed as: NEMAWARKAR SHASHANK · NEMAWARKAR SHASHANK S
33 granted patents·2 pending applications·415 citations·filing 1999–2023
97Inventor score
Top patents by PatentIndex Score
35 records- 0196US10282103B1Method and apparatus to delete a command queueSEAGATE TECHNOLOGY LLC·Filed 2016·Granted May 7, 2019·30 cites·19 claims
- 0296US9996262B1Method and apparatus to abort a commandSEAGATE TECHNOLOGY LLC·Filed 2015·Granted Jun 12, 2018·33 cites·20 claims
- 0395US11119691B1Method and apparatus to perform a function level reset in a memory controllerSEAGATE TECHNOLOGY LLC·Filed 2020·Granted Sep 14, 2021·6 cites·20 claims
- 0495US10572180B1Method and apparatus to perform a function level reset in a memory controllerSEAGATE TECHNOLOGY LLC·Filed 2016·Granted Feb 25, 2020·19 cites·19 claims
- 0590US11587601B1Apparatus and method for controlled transmitting of read pulse and write pulse in memoryGLOBALFOUNDRIES US INC·Filed 2021·Granted Feb 21, 2023·2 cites·20 claims
- 0689US7159137B2Synchronized communication between multi-processor clusters of multi-cluster computer systemsNEWISYS INC·Filed 2003·Granted Jan 2, 2007·62 cites·16 claims
- 0788US6965982B2Multithreaded processor efficiency by pre-fetching instructions for a scheduled threadIBM·Filed 2001·Granted Nov 15, 2005·61 cites·19 claims
- 0887US8638805B2Packet draining from a scheduling hierarchy in a traffic manager of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Jan 28, 2014·13 cites·20 claims
- 0986US8848723B2Scheduling hierarchy in a traffic manager of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Sep 30, 2014·11 cites·16 claims
- 1084US10620832B1Method and apparatus to abort a commandSEAGATE TECHNOLOGY LLC·Filed 2018·Granted Apr 14, 2020·3 cites·20 claims
- 1184US9160684B2Dynamic updating of scheduling hierarchy in a traffic manager of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Oct 13, 2015·9 cites·20 claims
- 1283US8547878B2Modularized scheduling engine for traffic management in a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Oct 1, 2013·8 cites·19 claims
- 1381US8869150B2Local messaging in a scheduling hierarchy in a traffic manager of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Oct 21, 2014·7 cites·21 claims
- 1481US7103823B2Communication between multi-processor clusters of multi-cluster computer systemsNEWISYS INC·Filed 2003·Granted Sep 5, 2006·34 cites·30 claims
- 1578US8869156B2Speculative task reading in a traffic manager of a network processorAULAKH SHAILENDRA·Filed 2011·Granted Oct 21, 2014·8 cites·16 claims
- 1677US10061655B2Volatile cache reconstruction after power failureSEAGATE TECHNOLOGY LLC·Filed 2016·Granted Aug 28, 2018·2 cites·21 claims
- 1776US8565250B2Multithreaded, superscalar scheduling in a traffic manager of a network processorNEMAWARKAR SHASHANK·Filed 2011·Granted Oct 22, 2013·5 cites·17 claims
- 1876US7117419B2Reliable communication between multi-processor clusters of multi-cluster computer systemsNEWISYS INC·Filed 2003·Granted Oct 3, 2006·22 cites·25 claims
- 1974US8576862B2Root scheduling algorithm in a network processorSONNIER DAVID·Filed 2011·Granted Nov 5, 2013·4 cites·17 claims
- 2074US7395347B2Communication between and within multi-processor clusters of multi-cluster computer systemsNEWISYS INC·Filed 2003·Granted Jul 1, 2008·20 cites·20 claims
- 2173US10169232B2Associative and atomic write-back caching system and method for storage subsystemSEAGATE TECHNOLOGY LLC·Filed 2016·Granted Jan 1, 2019·2 cites·18 claims
- 2268US8843682B2Hybrid address mutex mechanism for memory accesses in a network processorNEMAWARKAR SHASHANK·Filed 2011·Granted Sep 23, 2014·3 cites·20 claims
- 2365US8869151B2Packet draining from a scheduling hierarchy in a traffic manager of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Oct 21, 2014·2 cites·20 claims
- 2464US6651162B1Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cacheIBM·Filed 1999·Granted Nov 18, 2003·41 cites·21 claims
- 2562US12328880B2Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latencyGLOBALFOUNDRIES US INC·Filed 2023·Granted Jun 10, 2025·0 cites·20 claims
- 2661US7386626B2Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systemsNEWISYS INC·Filed 2003·Granted Jun 10, 2008·8 cites·30 claims
- 2760US12293086B2Apparatus and method for providing high throughput memory responsesGLOBALFOUNDRIES US INC·Filed 2023·Granted May 6, 2025·0 cites·19 claims
- 2859US11635958B1Multi-port register file for partial-sum accumulationGLOBALFOUNDRIES US INC·Filed 2022·Granted Apr 25, 2023·0 cites·18 claims
- 2955US12087384B2Bias voltage generation circuit for memory devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Sep 10, 2024·0 cites·16 claims
- 3055US11113063B2Method and apparatus to control the use of hierarchical branch predictors based on the effectiveness of their resultsSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Sep 7, 2021·0 cites·18 claims
- 3146US10310975B2Cache offload based on predictive power parameterSEAGATE TECHNOLOGY LLC·Filed 2016·Granted Jun 4, 2019·0 cites·19 claims
- 3246US2023186980A1Synthesizable logic memoryGLOBALFOUNDRIES US INC·Filed 2021·Application pending·0 cites
- 3343US10564865B2Lockless parity management in a distributed data storage systemSEAGATE TECHNOLOGY LLC·Filed 2016·Granted Feb 18, 2020·0 cites·20 claims
- 3441US2014254735A1Transmit reference signal cleanup within a synchronous network applicationLSI CORP·Filed 2013·Application pending·0 cites
- 3538US8837501B2Shared task parameters in a scheduler of a network processorSUNDARARAMAN BALAKRISHNAN·Filed 2011·Granted Sep 16, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →