Inventor · disambiguated record
Shyue Fong Quek
Also filed as: QUEK SHYUE FONG
33 granted patents·2 pending applications·1,019 citations·filing 1999–2014
98Inventor score
Files withCHARTERED SEMICONDUCTOR MFG30CHARTERED SEMINCONDUCTOR MFG L1GLOBALFOUNDRIES SG PTE LTD1LEE HUN CHOW1YANG QING1
Top patents by PatentIndex Score
35 records- 0198US6492726B1Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnectionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Dec 10, 2002·267 cites·28 claims
- 0293US6261917B1High-K MOM capacitorCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jul 17, 2001·78 cites·30 claims
- 0391US6406994B1Triple-layered low dielectric constant dielectric dual damascene approachCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 18, 2002·31 cites·20 claims
- 0490US6252290B1Method to form, and structure of, a dual damascene interconnect deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 26, 2001·123 cites·19 claims
- 0589US6611024B2Method of forming PID protection diode for SOI waferCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 26, 2003·44 cites·8 claims
- 0687US6303414B1Method of forming PID protection diode for SOI waferCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·42 cites·11 claims
- 0787US6275089B1Low voltage controllable transient trigger network for ESD protectionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 14, 2001·45 cites·10 claims
- 0884US6406948B1Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrateCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 18, 2002·33 cites·18 claims
- 0980US6376379B1Method of hard mask patterningCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 23, 2002·25 cites·26 claims
- 1077US6177324B1ESD protection device for STI deep submicron technologyCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 23, 2001·42 cites·24 claims
- 1176US6787422B2Method of body contact for SOI mosfetCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 7, 2004·20 cites·9 claims
- 1275US6416909B1Alternating phase shift mask and method for fabricating the alignment monitorCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jul 9, 2002·16 cites·25 claims
- 1374US6090691AMethod for forming a raised source and drain without using selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 18, 2000·46 cites·30 claims
- 1473US6582856B1Simplified method of fabricating a rim phase shift maskCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 24, 2003·13 cites·19 claims
- 1570US6376319B2Process to fabricate a source-drain extensionCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 23, 2002·13 cites·9 claims
- 1669US6963113B2Method of body contact for SOI MOSFETCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Nov 8, 2005·13 cites·14 claims
- 1767US6465296B1Vertical source/drain contact semiconductorCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 15, 2002·14 cites·16 claims
- 1866US6653674B2Vertical source/drain contact semiconductorCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Nov 25, 2003·11 cites·24 claims
- 1963US6248618B1Method of fabrication of dual gate oxides for CMOS devicesCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 19, 2001·22 cites·22 claims
- 2062US6486515B2ESD protection network used for SOI technologyCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Nov 26, 2002·9 cites·6 claims
- 2160US9064084B2Topography driven OPC and lithography flowGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jun 23, 2015·2 cites·22 claims
- 2260US6764914B2Method of forming a high K metallic dielectric layerCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 20, 2004·6 cites·8 claims
- 2360US6214680B1Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regionsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Apr 10, 2001·22 cites·29 claims
- 2458US6284609B1Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regionsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Sep 4, 2001·22 cites·27 claims
- 2553US6258677B1Method of fabricating wedge isolation transistorsCHARTERED SEMINCONDUCTOR MFG L·Filed 1999·Granted Jul 10, 2001·22 cites·19 claims
- 2651US6455384B2Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacersCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·4 cites·7 claims
- 2750US6803314B2Double-layered low dielectric constant dielectric dual damascene methodCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 12, 2004·5 cites·10 claims
- 2847US6399431B1ESD protection device for SOI technologyCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 4, 2002·3 cites·18 claims
- 2946US8898597B2Etch failure prediction based on wafer resist top lossYANG QING·Filed 2013·Granted Nov 25, 2014·0 cites·15 claims
- 3045US6100161AMethod of fabrication of a raised source/drain transistorCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 8, 2000·10 cites·14 claims
- 3138US6737739B2Method of vacuum packaging a semiconductor device assemblyCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted May 18, 2004·0 cites·16 claims
- 3238US6329253B1Thick oxide MOS device used in ESD protection circuitCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 11, 2001·9 cites·26 claims
- 3338US2013252350A1System and method for generating care areas for defect inspectionLEE HUN CHOW·Filed 2012·Application pending·0 cites
- 3437US6495399B1Method of vacuum packaging a semiconductor device assemblyCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 17, 2002·7 cites·19 claims
- 3537US2002048884A1Vertical source/drain contact semiconductorFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →