Inventor · disambiguated record
Shyam Ramji
Also filed as: RAMJI SHYAM
44 granted patents·4 pending applications·226 citations·filing 2002–2023
97Inventor score
Top patents by PatentIndex Score
48 records- 0195US7549137B2Latch placement for high performance and low power circuitsIBM·Filed 2006·Granted Jun 16, 2009·43 cites·12 claims
- 0292US8954912B2Structured placement of latches/flip-flops to minimize clock power in high-performance designsIBM·Filed 2012·Granted Feb 10, 2015·18 cites·25 claims
- 0390US9418188B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 16, 2016·5 cites·1 claims
- 0488US8782584B2Post-placement cell shiftingIBM·Filed 2013·Granted Jul 15, 2014·10 cites·1 claims
- 0587US9495501B1Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 15, 2016·4 cites·10 claims
- 0687US9436791B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2015·Granted Sep 6, 2016·4 cites·20 claims
- 0786US10803224B2Propagating constants of structured soft blocks while preserving the relative placement structureIBM·Filed 2018·Granted Oct 13, 2020·5 cites·20 claims
- 0886US10558775B2Memory element graph-based placement in integrated circuit designIBM·Filed 2017·Granted Feb 11, 2020·4 cites·17 claims
- 0986US7934188B2Legalization of VLSI circuit placement with blockages using hierarchical row slicingIBM·Filed 2008·Granted Apr 26, 2011·16 cites·18 claims
- 1085US8010926B2Clock power minimization with regular physical placement of clock repeater componentsIBM·Filed 2008·Granted Aug 30, 2011·15 cites·17 claims
- 1183US12423502B2Rule check heatmap predictionIBM·Filed 2022·Granted Sep 23, 2025·1 cites·20 claims
- 1283US9910952B2Hierarchically aware interior pinning for large synthesis blocksIBM·Filed 2016·Granted Mar 6, 2018·4 cites·20 claims
- 1382US9747400B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 29, 2017·2 cites·1 claims
- 1482US9703914B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Jul 11, 2017·2 cites·20 claims
- 1581US9858377B2Constraint-driven pin optimization for hierarchical design convergenceIBM·Filed 2015·Granted Jan 2, 2018·4 cites·19 claims
- 1681US8234615B2Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layoutRAMJI SHYAM·Filed 2010·Granted Jul 31, 2012·13 cites·20 claims
- 1780US10157255B2Hierarchically aware interior pinning for large synthesis blocksIBM·Filed 2017·Granted Dec 18, 2018·3 cites·18 claims
- 1879US8954915B2Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuitIBM·Filed 2013·Granted Feb 10, 2015·6 cites·12 claims
- 1979US8595675B1Local objective optimization in global placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Nov 26, 2013·5 cites·12 claims
- 2079US8495534B2Post-placement cell shiftingALPERT CHARLES J·Filed 2010·Granted Jul 23, 2013·5 cites·23 claims
- 2177US8347257B2Detailed routability by cell placementIBM·Filed 2010·Granted Jan 1, 2013·5 cites·24 claims
- 2275US7076755B2Method for successive placement based refinement of a generalized cost functionIBM·Filed 2004·Granted Jul 11, 2006·24 cites·15 claims
- 2372US10796064B2Autonomous placement to satisfy self-aligned double patterning constraintsIBM·Filed 2018·Granted Oct 6, 2020·1 cites·20 claims
- 2472US9519744B1Merging of storage elements on multi-cycle signal distribution trees into multi-bit cellsIBM·Filed 2015·Granted Dec 13, 2016·2 cites·20 claims
- 2571US10762271B2Model-based refinement of the placement process in integrated circuit generationIBM·Filed 2018·Granted Sep 1, 2020·1 cites·20 claims
- 2671US10635773B1Enhancing stability of half perimeter wire length (HPWL)-driven analytical placementIBM·Filed 2018·Granted Apr 28, 2020·1 cites·20 claims
- 2771US9053285B2Thermally aware pin assignment and device placementIBM·Filed 2013·Granted Jun 9, 2015·3 cites·18 claims
- 2869US7089521B2Method for legalizing the placement of cells in an integrated circuit layoutIBM·Filed 2004·Granted Aug 8, 2006·16 cites·19 claims
- 2964US9715572B2Hierarchical wire-pin co-optimizationIBM·Filed 2015·Granted Jul 25, 2017·1 cites·7 claims
- 3063US11080443B2Memory element graph-based placement in integrated circuit designIBM·Filed 2019·Granted Aug 3, 2021·0 cites·13 claims
- 3163US10685160B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2018·Granted Jun 16, 2020·0 cites·18 claims
- 3259US10210297B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Feb 19, 2019·0 cites·1 claims
- 3358US8347249B2Incremental timing optimization and placementIBM·Filed 2009·Granted Jan 1, 2013·1 cites·25 claims
- 3458US2025005326A1Reusing weights and biases in an artificial intelligence accelerator for a neural network for different minibatch sizes of inferencesIBM·Filed 2023·Application pending·0 cites
- 3557US11574249B2Streamlining data processing optimizations for machine learning workloadsIBM·Filed 2020·Granted Feb 7, 2023·0 cites·20 claims
- 3657US10140409B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 27, 2018·0 cites·5 claims
- 3756US8276105B2Automatic positioning of gate array circuits in an integrated circuit designKEINERT JOACHIM·Filed 2009·Granted Sep 25, 2012·1 cites·17 claims
- 3855US8930867B2Scheduling for parallel processing of regionally-constrained placement problemIBM·Filed 2013·Granted Jan 6, 2015·0 cites·11 claims
- 3955US8245173B2Scheduling for parallel processing of regionally-constrained placement problemNAM GI-JOON·Filed 2009·Granted Aug 14, 2012·1 cites·2 claims
- 4054US2024419401A1Artificial intelligence accelerator using mantissa quantization schemeIBM·Filed 2023·Application pending·0 cites
- 4149US8578315B2Scheduling for parallel processing of regionally-constrained placement problemNAM GI-JOON·Filed 2012·Granted Nov 5, 2013·0 cites·7 claims
- 4248US10891411B2Hierarchy-driven logical and physical synthesis co-optimizationIBM·Filed 2018·Granted Jan 12, 2021·0 cites·20 claims
- 4348US9697322B2Hierarchical wire-pin co-optimizationIBM·Filed 2015·Granted Jul 4, 2017·0 cites·12 claims
- 4446US8769457B2Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Jul 1, 2014·0 cites·18 claims
- 4542US10216882B2Critical path straightening system based on free-space aware and timing driven incremental placementIBM·Filed 2016·Granted Feb 26, 2019·0 cites·17 claims
- 4641US2012297355A1Whitespace creation and preservation in circuit designALPERT CHARLES JAY·Filed 2011·Application pending·0 cites
- 4740US2003217338A1Congestion mitigation with logic order preservationIBM·Filed 2002·Application pending·0 cites
- 4837US8683411B2Electronic design automation object placement with partially region-constrained objectsALPERT CHARLES J·Filed 2010·Granted Mar 25, 2014·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →