Inventor · disambiguated record
Shailesh Shah
Also filed as: SHAH SHAILESH · SHAH SHAILESH I
16 granted patents·2 pending applications·404 citations·filing 1994–2024
95Inventor score
Top patents by PatentIndex Score
18 records- 0198US11620256B2Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2022·Granted Apr 4, 2023·36 cites·22 claims
- 0293US2025103548A1Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2024·Application pending·0 cites
- 0390US12210477B2Systems and methods for improving cache efficiency and utilizationINTEL CORP·Filed 2020·Granted Jan 28, 2025·2 cites·20 claims
- 0485US6523055B1Circuit and method for multiplying and accumulating the sum of two products in a single cycleLSI LOGIC CORP·Filed 1999·Granted Feb 18, 2003·142 cites·24 claims
- 0584US5835401ADram with hidden refreshCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Nov 10, 1998·64 cites·15 claims
- 0682US7221200B1Programmable low voltage reset apparatus for multi-Vdd chipsCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted May 22, 2007·17 cites·19 claims
- 0778US6822899B1Method of protecting flash memory from data corruption during fast power down eventsCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Nov 23, 2004·33 cites·20 claims
- 0874US9075741B2Dynamic error handling using parity and redundant rowsKOKER ALTUG·Filed 2011·Granted Jul 7, 2015·4 cites·4 claims
- 0968US7170179B1Chip select method through double bondingCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Jan 30, 2007·15 cites·19 claims
- 1064US5559465AOutput preconditioning circuit with an output level latch and a clampCYPRESS SEMICONDUCTOR CORP·Filed 1994·Granted Sep 24, 1996·19 cites·15 claims
- 1156US5490115AMethod and apparatus for writing to memory cells in a minimum number of cycles during a memory test operationCYPRESS SEMICONDUCTOR CORP·Filed 1994·Granted Feb 6, 1996·17 cites·28 claims
- 1250US5835970ABurst address generator having two modes of operation employing a linear/nonlinear counter using decoded addressesCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Nov 10, 1998·24 cites·21 claims
- 1344US5933032AApparatus and method for generating a pulse signalCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Aug 3, 1999·8 cites·22 claims
- 1443US5903174AMethod and apparatus for reducing skew among input signals within an integrated circuitCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted May 11, 1999·7 cites·20 claims
- 1538US6222393B1Apparatus and method for generating a pulse signalCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Apr 24, 2001·5 cites·4 claims
- 1636US5987603AApparatus and method for reversing bits using a shifterLSI LOGIC CORP·Filed 1997·Granted Nov 16, 1999·9 cites·8 claims
- 1735US2013346926A1Automatic optimal integrated circuit generator from algorithms and specificationALGOTOCHIP CORP·Filed 2012·Application pending·0 cites
- 1831US5652732AApparatus and method for matching a clock delay to a delay through a memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Jul 29, 1997·2 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →