Inventor · disambiguated record
Shogo Shibazaki
Also filed as: SHIBAZAKI SHOGO
12 granted patents·552 citations·filing 1994–2009
93Inventor score
Top patents by PatentIndex Score
12 records- 0197US6125424AMethod of writing, erasing, and controlling memory and memory device having erasing and moving componentsFUJITSU LTD·Filed 1998·Granted Sep 26, 2000·148 cites·29 claims
- 0297US5802551AMethod and apparatus for controlling the writing and erasing of information in a memory deviceFUJITSU LTD·Filed 1994·Granted Sep 1, 1998·200 cites·12 claims
- 0392US6766409B2Method of writing, erasing, and controlling memory for memory deviceFUJITSU LTD·Filed 2003·Granted Jul 20, 2004·43 cites·4 claims
- 0490US5983312ASimultaneously writing to and erasing two commonly numbered sectorsFUJITSU LTD·Filed 1997·Granted Nov 9, 1999·53 cites·4 claims
- 0587US6161163AMethod of writing, erasing, and controlling memory for memory deviceFUJITSU LTD·Filed 1999·Granted Dec 12, 2000·42 cites·3 claims
- 0680US7689836B2Encryption deviceFUJITSU MICROELECTRONICS LTD·Filed 2005·Granted Mar 30, 2010·11 cites·8 claims
- 0780US7076667B1Storage device having secure test processFUJITSU LTD·Filed 2000·Granted Jul 11, 2006·31 cites·10 claims
- 0864US6625712B2Memory management table producing method and memory deviceFUJITSU LTD·Filed 2001·Granted Sep 23, 2003·10 cites·17 claims
- 0939US6118312AClock switch circuitFUJITSU LTD·Filed 1999·Granted Sep 12, 2000·5 cites·9 claims
- 1036US5809257ABus control apparatus for data transfer systemFUJITSU LTD·Filed 1996·Granted Sep 15, 1998·9 cites·10 claims
- 1132US8143901B2Test apparatus, test method, and integrated circuitDEGUCHI CHIKAHIRO·Filed 2009·Granted Mar 27, 2012·0 cites·8 claims
- 1228US8503259B2Memory test method and memory test deviceSHIBAZAKI SHOGO·Filed 2009·Granted Aug 6, 2013·0 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →