Inventor · disambiguated record
Shalesh Thusoo
Also filed as: THUSOO SHALESH
20 granted patents·1,418 citations·filing 1995–2005
97Inventor score
Top patents by PatentIndex Score
20 records- 0195US6934832B1Exception mechanism for a computerATI INT SRL·Filed 2000·Granted Aug 23, 2005·152 cites·71 claims
- 0294US6941545B1Profiling of computer programs executing in virtual memory systemsATI INT SRL·Filed 1999·Granted Sep 6, 2005·171 cites·81 claims
- 0392US7013456B1Profiling execution of computer programsATI INT SRL·Filed 1999·Granted Mar 14, 2006·188 cites·45 claims
- 0491US5848264ADebug and video queue for multi-processor chipS3 INC·Filed 1996·Granted Dec 8, 1998·204 cites·20 claims
- 0590US7228404B1Managing instruction side-effectsATI INT SRL·Filed 2000·Granted Jun 5, 2007·66 cites·52 claims
- 0689US8065504B2Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processorYATES JR JOHN S·Filed 2004·Granted Nov 22, 2011·56 cites·27 claims
- 0781US6449671B1Method and apparatus for busing data elementsATI INT SRL·Filed 1999·Granted Sep 10, 2002·97 cites·24 claims
- 0880US6826748B1Profiling program execution into registers of a computerATI INT SRL·Filed 1999·Granted Nov 30, 2004·77 cites·27 claims
- 0978US5687336AStack push/pop tracking and pairing in a pipelined processorEXPONENTIAL TECHN INC·Filed 1996·Granted Nov 11, 1997·84 cites·19 claims
- 1073US5822602APipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacityS3 INC·Filed 1996·Granted Oct 13, 1998·69 cites·13 claims
- 1168US5632028AHardware support for fast software emulation of unimplemented instructionsHAL COMPUTER SYSTEMS INC·Filed 1995·Granted May 20, 1997·55 cites·6 claims
- 1263US5790443AMixed-modulo address generation using shadow segment registersS3 INC·Filed 1996·Granted Aug 4, 1998·45 cites·19 claims
- 1360US5809272AEarly instruction-length pre-decode of variable-length instructions in a superscalar processorEXPONENTIAL TECHN INC·Filed 1995·Granted Sep 15, 1998·39 cites·19 claims
- 1456US5790826AReduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writesS3 INC·Filed 1996·Granted Aug 4, 1998·32 cites·20 claims
- 1555US6430646B1Method and apparatus for interfacing a processor with a busATI INT SRL·Filed 1999·Granted Aug 6, 2002·29 cites·44 claims
- 1645US6775756B1Method and apparatus for out of order memory processing within an in order processorATI INT SRL·Filed 1999·Granted Aug 10, 2004·18 cites·16 claims
- 1744US6389519B1Method and apparatus for providing probe based bus locking and address lockingATI INT SRL·Filed 1999·Granted May 14, 2002·15 cites·28 claims
- 1841US6643726B1Method of manufacture and apparatus of an integrated computing systemATI INT SRL·Filed 1999·Granted Nov 4, 2003·13 cites·14 claims
- 1933US6578134B1Multi-branch resolutionATI INT SRL·Filed 1999·Granted Jun 10, 2003·8 cites·4 claims
- 2032US7240255B2Area efficient BIST system for memoriesCISCO TECH INC·Filed 2005·Granted Jul 3, 2007·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →