Inventor · disambiguated record
Shahin Toutounchi
Also filed as: TOUTOUNCHI SHAHIN
30 granted patents·819 citations·filing 1992–2010
98Inventor score
Top patents by PatentIndex Score
30 records- 0195US7302625B1Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfigurationXILINX INC·Filed 2005·Granted Nov 27, 2007·79 cites·12 claims
- 0295US6266269B1Three terminal non-volatile memory elementXILINX INC·Filed 2000·Granted Jul 24, 2001·113 cites·19 claims
- 0392US6817006B1Application-specific testing methods for programmable logic devicesXILINX INC·Filed 2002·Granted Nov 9, 2004·51 cites·25 claims
- 0491US7761755B1Circuit for and method of testing for faults in a programmable logic deviceXILINX INC·Filed 2007·Granted Jul 20, 2010·25 cites·20 claims
- 0591US6891395B2Application-specific testing methods for programmable logic devicesXILINX INC·Filed 2004·Granted May 10, 2005·43 cites·16 claims
- 0690US6044012ANon-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS processXILINX INC·Filed 1999·Granted Mar 28, 2000·81 cites·13 claims
- 0787US7917820B1Testing an embedded coreXILINX INC·Filed 2008·Granted Mar 29, 2011·31 cites·19 claims
- 0887US7219287B1Automated fault diagnosis in a programmable deviceXILINX INC·Filed 2004·Granted May 15, 2007·36 cites·30 claims
- 0987US6268639B1Electrostatic-discharge protection circuitXILINX INC·Filed 1999·Granted Jul 31, 2001·64 cites·22 claims
- 1086US6594610B1Fault emulation testing of programmable logic devicesXILINX INC·Filed 2001·Granted Jul 15, 2003·36 cites·24 claims
- 1185US8311762B1Manufacturing test for a programmable integrated circuit implementing a specific user designHARTANTO ISMED D·Filed 2010·Granted Nov 13, 2012·7 cites·17 claims
- 1282US5220192ARadiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereofLSI LOGIC·Filed 1992·Granted Jun 15, 1993·66 cites·12 claims
- 1381US7544968B1Non-volatile memory cell with charge storage element and method of programmingXILINX INC·Filed 2005·Granted Jun 9, 2009·8 cites·13 claims
- 1481US6549458B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2001·Granted Apr 15, 2003·25 cites·23 claims
- 1577US6645802B1Method of forming a zener diodeXILINX INC·Filed 2001·Granted Nov 11, 2003·20 cites·6 claims
- 1676US6522582B1Non-volatile memory array using gate breakdown structuresXILINX INC·Filed 2000·Granted Feb 18, 2003·20 cites·39 claims
- 1771US7725787B1Testing of a programmable deviceXILINX INC·Filed 2008·Granted May 25, 2010·5 cites·20 claims
- 1871US6982451B1Single event upset in SRAM cells in FPGAs with high resistivity gate structuresXILINX INC·Filed 2003·Granted Jan 3, 2006·15 cites·12 claims
- 1971US6732309B1Method for testing faults in a programmable logic deviceXILINX INC·Filed 2001·Granted May 4, 2004·15 cites·5 claims
- 2069US7687797B1Three-terminal non-volatile memory element with hybrid gate dielectricXILINX INC·Filed 2005·Granted Mar 30, 2010·3 cites·14 claims
- 2168US7452765B1Single event upset in SRAM cells in FPGAs with high resistivity gate structuresXILINX INC·Filed 2005·Granted Nov 18, 2008·3 cites·11 claims
- 2263US7420842B1Method of programming a three-terminal non-volatile memory element using source-drain biasXILINX INC·Filed 2005·Granted Sep 2, 2008·5 cites·10 claims
- 2363US6920621B1Methods of testing for shorts in programmable logic devices using relative quiescent current measurementsXILINX INC·Filed 2003·Granted Jul 19, 2005·9 cites·25 claims
- 2459US6732348B1Method for locating faults in a programmable logic deviceXILINX INC·Filed 2001·Granted May 4, 2004·10 cites·20 claims
- 2555US7450431B1PMOS three-terminal non-volatile memory element and method of programmingXILINX INC·Filed 2005·Granted Nov 11, 2008·3 cites·6 claims
- 2651US7947980B1Non-volatile memory cell with charge storage element and method of programmingXILINX INC·Filed 2009·Granted May 24, 2011·0 cites·11 claims
- 2750US5516731AHigh-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistanceLSI LOGIC CORP·Filed 1994·Granted May 14, 1996·21 cites·12 claims
- 2847US7454675B1Testing of a programmable deviceXILINX INC·Filed 2004·Granted Nov 18, 2008·3 cites·16 claims
- 2946US5661069AMethod of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve spaceLSI LOGIC CORP·Filed 1995·Granted Aug 26, 1997·10 cites·1 claims
- 3041US5561319AIntegrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereofLSI LOGIC CORP·Filed 1994·Granted Oct 1, 1996·12 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →