Inventor · disambiguated record
Shinichiro Yamaguchi
Also filed as: YAMAGUCHI SHINICHIRO
15 granted patents·514 citations·filing 1986–2001
95Inventor score
Technology areasG06F
Files withHITACHI LTD15
Top patents by PatentIndex Score
15 records- 0187US4811269ABit slice multiplication circuitHITACHI LTD·Filed 1986·Granted Mar 7, 1989·95 cites·4 claims
- 0286US4839846AApparatus for performing floating point arithmetic operations and rounding the result thereofHITACHI LTD·Filed 1986·Granted Jun 13, 1989·91 cites·10 claims
- 0375US5852728AUninterruptible clock supply apparatus for fault tolerant computer systemHITACHI LTD·Filed 1996·Granted Dec 22, 1998·76 cites·4 claims
- 0465US5841963ADual information processing system having a plurality of data transfer channelsHITACHI LTD·Filed 1997·Granted Nov 24, 1998·51 cites·1 claims
- 0562US5003458ASuspended instruction restart processing system based on a checkpoint microprogram addressHITACHI LTD·Filed 1987·Granted Mar 26, 1991·31 cites·3 claims
- 0659US6453391B2Multiplexed computer systemHITACHI LTD·Filed 2001·Granted Sep 17, 2002·7 cites·4 claims
- 0756US6003116AMultiplexed computer system with the capability to copy data from one processor memory to anotherHITACHI LTD·Filed 1996·Granted Dec 14, 1999·32 cites·4 claims
- 0854US5146569ASystem for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspensionHITACHI LTD·Filed 1991·Granted Sep 8, 1992·29 cites·9 claims
- 0950US4841439AMethod for restarting execution interrupted due to page fault in a data processing systemHITACHI LTD·Filed 1986·Granted Jun 20, 1989·18 cites·4 claims
- 1049US4764869AMethod and apparatus for controlling interruption in the course of instruction execution in a processorHITACHI LTD·Filed 1986·Granted Aug 16, 1988·17 cites·10 claims
- 1147US4896258AData processor provided with instructions which refer to both tagged and tagless dataHITACHI LTD·Filed 1986·Granted Jan 23, 1990·16 cites·21 claims
- 1242US6032265AFault-tolerant computer systemHITACHI LTD·Filed 1996·Granted Feb 29, 2000·18 cites·9 claims
- 1341US4967339AOperation control apparatus for a processor having a plurality of arithmetic devicesHITACHI LTD·Filed 1988·Granted Oct 30, 1990·11 cites·4 claims
- 1439US5517669ACyclic data communication systemHITACHI LTD·Filed 1994·Granted May 14, 1996·12 cites·19 claims
- 1532US5737513AMethod of and system for verifying operation concurrence in maintenance/replacement of twin CPUsHITACHI LTD·Filed 1996·Granted Apr 7, 1998·10 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →